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The Low Power Design Community recently published a nice summary of the techniques folks use to control leakage power, from the process-level to architectural:
And our own Steve Carlson is heavily quoted!
Actually, one key point I would like to echo is the one about excessive performance margin. We still see a lot of this. Too much. Folks over-margining their timing constraints by 30-40% because of the uncertainty of physical interconnect. At 65nm, increasing performance by 30% will increase leakage by 100%...do you really want to do that for your entire design? And does it even help all the cases where you have large delays due to a long wire going across the chip?
The better answer is to use a tool like RC-Physical, that uses production placement in the production floorplan, and brings that info into the synthesis process. This enables synthesis to optimize the truly difficult paths for timing, and the rest for power and area.
Excessively margining for one metric is no longer an option in today's process geometries, and for that matter in today's competitive semi market.
Yeah, I'd think you'd want to set your constraints reasonably, and not just squeeze on one constraint (over-constraining timing) but timing, area and power...and have the Synthesis tool work to achieve those simultaneously!