Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
By Diego Hammerschlag
Sr. Technical Leader
Most, if not all, synthesis tools today support the use of Synopsys
DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare,
Cadence's ChipWare and others. I have been frequently asked on the purpose of
<vendor>Ware being that many of the functions implemented by DesignWare
and its derivatives are readily supported by the tools today using much simpler
higher level constructs.
<vendor>Ware is used primarily in the following situations:
I will first cover (2), (3), and (4) while (1) will be covered later in more detail
(2) Reduce implementation time & risk for modules with limited or no
<vendor>Ware not only covers simple design that can be easily coded
using higher level constructs, but it also includes slightly more complex
designs such as Error Code Correction(ECC), Cyclic Redundancy Checker(CRC), as
well as others. These types of designs are well defined and well understood and
frequently provide little opportunity for companies to differentiate their
product hence it is sometimes attractive for users to take advantage of the
pre-implemented benefits of <vendor>Ware. Not only that, but one could
argue, and EDA vendors certainly do, that the reuse of such designs by many
customers results in less likelihood of bugs and issues with their
(3) Purchased IP
Several vendors also market larger IP as <vendor>Ware. This is
slightly different than what (1) and (2) cover. It refers to larger designs as
well as associated verification environments or additional verification IP.
This kind of vendor<Ware> includes PCI cores, USB cores, and others.
These kinds of <vendor>Ware can have a substantial cost associated with
(4) Legacy support
Frequently <vendor>Ware is used and supported as a result of legacy
designs and usage in third party IP
(1) To address shortcomings of the tools and/or specifications
To understand the main purpose of <vendor>Ware we need to go back some
time. Early synthesis technology did a poor job, or was simply not capable, of
optimizing datapath components such as adders and multipliers. Moreover,
standards like IEEE1364-1995(Verilog HDL) did not have comprehensive support of
signed arithmetic at the time. As a result, coding certain operations may have
been cumbersome and error-prone at times. EDA vendors came up with
<vendor>Ware to address these shortcomings in their tools and the
specifications of the time. <vendor>Ware essentially addressed the issue
by hard-coding and parametrizing certain operations. The recent
"designWare minpower" announcement by Synopsys is a good illustration
of an application of the <vendor>Ware solution. In that case,
<vendor>Ware addresses Design Compiler's power optimization
When & Why to Avoid <vendor>Ware?
<vendor>Ware was an adequate solution at the time but it has several
EDA vendors would love you to use their brand of <vendor>Ware (DesignWare,
AmbitWare, etc.) since to a large extent, it ties your implementation to their
Equivalence checking challenges:
It is a well-documented issue that equivalency checking is a weakness of
the <vendor>Ware solution. Vendors normally provide a behavioral model
for functional verification as well as logic equivalency. This model is
different from the synthesis model used internally by the tools and hence there
is always a chance for non-equivalency issues.
Another aspect of <vendor>Ware
that can present challenges is that of ECOs since the synthesis model is, from
a user perspective, a black box hence making it difficult (or impossible in
some cases) for a user to implement and verify an ECO.
It is unnecessary!!!
Modern synthesis tools have addressed the original challenges, and coding
without the use of vendor<Ware> allows the tools the greatest degree of
flexibility to optimize. Modern synthesis tools can perform complex CSA
transformations, speculation, and many other optimizations. By keeping coding
at a higher level, the tool has more flexibility to optimize in the context of
the overall design goals and the surrounding logic and therefore yielding
better results. A frequently overlooked aspect of <vendor>Ware is highlighted
by "DesignWare minPower" - the original <vendor>Ware was not
created with power in mind so now you have to manually choose if you want the
version that gives the best area or the one that gives the best power. Higher
level constructs do not have this issue since the tools will optimize according
to the goals specified by the user as well as the context of where it is used.
The main benefits of avoiding <vendor>Ware are:
Please send me your comments and questions if you have any.
Good luck with your project.