Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates. It is easy if you are estimating at the chip-level and most of the power is consumed by macros and I/O's, since those vary very little. On the other hand you would want to make this measurement before you start developing RTL, so you can decide whether or not you need to choose different macros, IP, or libraries. A tool like Cadence's InCyte Chip Estimator is perfect for that.
But what about pure RTL estimation? As geometries shrink, obtaining reasonably accurate estimates gets more difficult. Power consumption varies more widely depending on cell sizing or choice of voltage thresholds. And those variables depend entirely on the timing criticality of the logic, and in smaller geometries that is more dependent on wire delays. Thus it is impossible to estimate power consumption without understanding the design's timing and how the synthesis tool will structure the logic.
This is why we built RTL power estimation right into RTL Compiler synthesis. Yes, it is built right-in, no extra license. The thinking was that we are providing power feedback to aid in RTL development, much in the way synthesis provides timing and area feedback. And you can annotate power consumption back to the RTL. To get going, you'll first want to enable the RTL cross-probing with this attribute:
set_attribute hdl_track_filename_row_col true /
Then you need to build the RTL power models. This of course uses your full SDC and utilizes the global synthesis engines so that the estimation is aware of how the logic will be structured and mapped for timing. The command to build the RTL power models is:
build_rtl_power_models [-clean_up_netlist] [-clock_gating_logic] [-relative instances] [-design design
In most cases you would want to use those first two options. The third option adds some runtime, but understanding relative power usage by hierarchy is often the most important metric at this stage.
Finally, to report power, the command is:
report power -rtl_cross_reference [-detail] [-flat ] [> file]
For those of you that use some form of RTL power estimation, Cadence or not, what are you using it for? To feed back power usage to designers? To regress power consumption at the chip level? Leakage? Switching? Both? etc.