Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Shutting down functional blocks is a great technique to reduce
power, there are many blocks that cannot be shut down long enough to deliver
power savings that justifies the associated overhead of this technique.
One under-utilized technique is reducing supply voltage on
domains that have performance margin. This can significantly reduce active
power - and leakage as well - and does not require any additional functional
verification. However it is difficult to figure out which domains can have
their voltages reduced, and by how much, and still meet timing. There just
isn't enough time to run all the experiments necessary to figure it out,
especially if your synthesis methodology is bottom-up. This is why we developed
Design Explorer (aka "DEX")
in RTL Compiler. We're starting to see some results now:
This design targets a 65nm multi-vt library. The default
synthesis flow used a single 1.08v domain. By creating an extra domain and
letting DEX explore both domains across 0.8v, 0.9v, and 1.08v (so, that's 32,
or 9 exploration runs), we found that this design could meet timing with one of
the domains at 1.08v and one at 0.8v. This resulted in a 51% reduction in
active power and a 60% reduction in leakage, with a 1% area increase, and
again, same performance. That's a pretty significant ROI.
Wired networking chip
This chip's performance target is aggressive and cannot
leverage shutting down blocks. It targets a 45nm multi-vt library, and had been
only using a single 1.08v domain. Partitioning the major functional blocks into
power domains resulted in a total of 3 domains. Letting DEX explore across 4
libraries - 0.8v, 0.9v, 0.99v, and 1.08v - means that it explored 64 different
scenarios in parallel. The scenario that best balanced performance with area
with power savings was one in which one domain was at 1.08v, one at 0.9v, one
at 0.99v, and one at 0.8v. This delivered an active power savings of 17%, a
leakage power savings of 29%, at a cost of a 1% area increase. Timing was -10ps
in this scenario, but that was deemed to be close enough that it could be
closed in physical implementation.
Another high-performance 65nm chip, this one was already
utilizing a multi-supply approach. However there were only 2 power domains, one
at 1.1v and the other at 0.9v. This was a conservative approach to save some
power while ensuring that performance would still be able to be met. For the
DEX explorations, we carved out two additional power domains, and explored
across 0.75v, 0.9v, and 1.1v. DEX explored across 81 different scenarios (4
domains, 3 voltages)! The scenario that delivered the desired balance of
performance, power, and area had the 1.1v domain remaining at 1.1v, and the
other three were able to meet timing at 0.75v. Area increased by 2% in this
scenario, but active power decreased by 36%, and leakage decreased by 89%!
These are just some examples of the type of extensive automatic
exploration that can be performed with DEX. You can see that the number of
power domains in each case was still small, in order to minimize the physical
implementation overhead. Yet the power savings achieved was still great. So how
much power are you leaving on the table by not doing this type of exploration?