Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. It also goes on to describe the verification problem of chips this size.
It is clear that synthesis needs to work in conjunction with placement. This is why we have over 50 customers now using our RTL Compiler Physical solution, which combines high-capacity global synthesis with production placement and fast routing estimation technology. This enables RTL Compiler's unique global synthesis to work in conjunction with real physical interconnect timing to speed closure to your overall performance, power, and area goals. And it can even prevent or fix congestion issues.
But what about those chips that are 20M gates or larger? Our experiences with RC show that it's runtimes scale linearly with design size, and we have had designers run artificial testcases of 20M instances (1 instance =~ 4 gates). But in production? We find that most teams like to match their synthesis runs to their physical partitions. Otherwise if you synthesize at a higher capacity, you'll need to partition your constraints afterwards. And we're constantly told that nobody waits until they have 20M gates-equivalent of RTL before they start synthesis. What is your approach?
The biggest challenge here is verification - functional verification consumes typically 60% of a chip project's hardware engineering costs. How do you verify 20M gates-equivalent of RTL? I think we are going to find that the answer is "you don't". The way to verify a chip this large is to move up a level of abstraction to Transaction Level Modeling (TLM) using a language like SystemC. I can't give a better argument for this than the experiences that Casio had, improving their verification/debug cycle by 50% using Cadence's C-to-Silicon, which includes RTL Compiler under-the-hood to bridge the flow from SystemC to implementation.
This is very similar to the crossroads that the industry faced two decades ago when it was becoming too cumbersome to design and simulate hundreds of thousands of gates at the gate-level. The solution was not to re-tool schematic capture and simulation - we moved up a level of abstraction. We need to change our mindset from incrementally tweaking the RTL-GDSII flow and re-define the problem as TLM-GDSII.