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At a macro level EDA360
is about driving the semiconductor industry toward sustainable differentiation.
It represents a Cadence mission to help its customers' customers achieve
industry leadership and profitability through enabling technologies,
methodologies, and services. Ultimately it is a charter for driving a
global community forward in a transforming economic environment.
This new charter, significant as it is, relies on
fundamental changes in organizational philosophy and activity -- moving from
separate and distinct goals to those with more symphonic momentum, clarity, and
direction. Organizational transformation is necessary for providing
industry enablement, and it comes at a time when semiconductor manufacturing
Law) faces its most challenging obtacles. It's a time when semiconductor
technology nodes, required for meeting today's functionality and software
application demands, are behaviorally impacted by atomic level uncertainties.
Given these lofty yet rational challenges and goals, it's no
wonder some might question where IC Test, or silicon verification, falls within
this charter. Why and how is IC Test impacted? And what changes are
necessary regarding how we think about and develop IC Test solutions?
The Dawning Of IC Test as a Differentiator
EDA360 represents the dawning of
IC Test as an essential component to enabling differentiation and
profitability. It marks the enablement of more complex, hierarchical
testing methodologies for IP, memory, block, and chip level design with greater
predictably. Within the context of silicon verification, it is an
assurance that only the highest quality devices with the lowest defect count
(DPPM) are produced profitably.
At an IEEE test symposium in 2008, Phil Nigh of IBM stated "The
role of IC testing is changing from being viewed as mainly a non-value (cost)
operation, to one which provides additional value to products." The value
of test is analogous to a piston within an engine -- it is power producing.
Without it fully integrated and firing, the engine's performance is inefficient
and will ultimately fail.
With consumer markets driving increasing volumes, decreasing
profit windows, and application-driven differentiation, finding and in fact traveling
the road to "zero" defects has never been more important. With
at-speed physically-aware test methodologies dominant, power-aware ATPG under
adoption, and process-aware ATPG on the horizon, the highest levels of tool
integration, automation, and downstream predictability for both physical design
and test design flows are required for SoC and Silicon Realization.
Economies of Thought Leadership
and the Age of a New Enlightenment
To accomplish all this
successfully, organizations and their contributors must likewise adopt
mind-sets of far greater coordination and integration, and move beyond
economies of scale to economies of technological thought leadership.
These transformations are most welcome at a time when design complexity, IP
reuse, growing memory requirements, and high quality silicon are absolute
building blocks for enabling differentiating software applications and
What does EDA360 mean for test and the test community? It
marks an overdue age of enlightenment.