Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Quality of Silicon improvements. A lot of work continues to go
into improving results, especially physical results. We have seen some early-adopter
partners gain some significant area, timing, and power savings (these tend to
be design-dependent and constraint-dependent, of course).
Multi-vt algorithm improvements.
We have done a lot of work in the multi-vt engine to deliver the best balance
of all your design goals. With 10.1.100, the low-effort multi-vt setting will
now focus on minimizing leakage power with no area penalty. Medium and high
efforts will still prioritize leakage optimization over area, and these effort
levels have seen reductions in leakage power versus previous releases. And the default
multi-vt effort setting is now medium-effort.
Runtime improvements for large
designs. This continues to be a focus area for the team, as the size of
designs being synthesized is growing. RC comfortably turns around 1M instances (that's
3-4M gates) overnight, and we are looking to speed things up even more for 1M+
Floorplan tweaking. When you
identify an issue in RC-Physical that is floorplan-related, wouldn't it be nice
to be able to try tweaking something in the floorplan yourself to see if it helps?
This should help speed up resolution of these types of issues, since you don't
have to bother the physical design team and wait for them to get a chance to
make the change.
Rapid re-synthesis. This is a new
capability in RC-GXL that speeds up turnaround time when trying different
things on the same design. So after you synthesize a design and want to change
a constraint, or attribute, or RTL; as long as the change is fairly localized,
the turnaround time will be much shorter than a full re-synthesis.
Superthreading no longer requires
GXL. Again on the faster turnaround theme, we want everybody running RC as
fast as possible! So superthreading no longer requires an RC-GXL key to enable
DFT. We have done a lot of work over the past 18 months to make test logic insertion work seamlessly within synthesis. Now that we feel it is
well-integrated, we are starting to build out the feature set some more. This
release features improved power estimation of test logic with the "report_test_power"
command. It also adds the ability to insert asymmetric compression logic to
reduce pin count in compression mode. And finally you can insert MBIST that can
be accessed directly without having to go through the TAP.
Those are the major items -- there are a lot of smaller improvements as well.
And we have more planned for the second half of the year, so stay tuned. We
will be doing update training throughout the second half of the year, so please
contact your local Cadence synthesis expert for details or input/feedback on
Once you purchase a license, you can download it and use it. Here is the contact form for getting in touch with sales in order to purchase: www.cadence.com/.../rpi.aspx