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Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs, whether they are related to bug fixes (those 'oh oh' moments of silence), or intended functional changes (which are not out of the ordinary -- maybe your marketing department has requested the design team to add a new feature to the ASIC because of competitive pressures). Thus, planning for ECOs is a necessity for any solid ASIC flow.
Let's take a step back. If you are unaware of what the term "ECO" means, in the ASIC world, it is defined as the "Engineering Change Order". In simple terms, it is a change to your design, whether it be functional, timing, or electrically related. In our case we are going to focus on functional logic design changes, since it is historically a big challenge to make them predictable, according to customer experiences. By the way, ECO is an acronym widely known and used because it is that common (and painful). ECOs hurt by reducing overall team productivity if not planned for carefully.
Being prepared to perform ECO functions is a necessity today because:
(1) Designers can make mistakes, and verification people can also make mistakes (missing design errors). We are all human, so we need plan for that.
(2) People make mistakes for all kinds of reasons, one reason being that designs are becoming more complex so verification coverage becomes more challenging (i.e. possibilities for missed coverage increases).
(3) Competitive pressures can correlate to higher occurrences of ECOs for a given design. In other words, design teams are being pushed to the limits with less time to verify due to tighter schedules, especially for ASIC products where time-to-market is critical.
(4) In additional, as mentioned above, competitive pressures can also lead to design specification changes, occurring dynamically during the implementation of the ASIC. Thus project scheduling may no longer be static and predictable, and must dynamically adjust to ever-changing design needs to produce the end ASIC product on time.
Now comes the question: "Can we plan for success under these conditions?"
The answer is a solid "Yes"- and Cadence technologies can help deliver solutions to meet these challenges.
In an exciting announcement January 31, Cadence released a flow to provide a digital end-to-end solution, with ECO automation as part of the flow. (You can read a nice summary in Wei Lii Tan's recent blog post). This work was a result of listening to customers and understanding what they needed to meet their ever growing challenges. Specifically, Cadence Conformal ECO Designer is leveraged in the digital end-to-end flow to help translate the designer's intent, abstract the issue at a level that the designer can understand and manage, and help implement and converge on a solution to meet the digital ASIC's requirements. What is exciting about Conformal ECO Designer is that it provides superior automation capabilities that can greatly reduce turnaround time for ECOs, thus increasing designer productivity, and in parallel play a role in increasing schedule predictability.
What we have seen with some customers is changed behavior when it comes to planning for ECOs. They actually embrace and budget for an increased number of ECOs that can be allocated in a shorter time, because of the confidence they have in Cadence's ECO technologies.
One week ago, while visiting a customer, one designer made this comment:
"With the option of leveraging Conformal ECO Designer automation capabilities, our management expects us to do more ECOs -- faster."
Wow -- that's a bold statement, and it could only be made because of the high confidence our customers have. In the context of a the full blown digital end-to-end solution, Conformal ECO Designer works in conjunction with a number of Cadence leading edge technologies.
(1) Conformal Logic Equivalency Checking (a.k. a. LEC), in order to set the foundation for analyzing the ECO changes. Conformal LEC has been the standard for logic equivalency checking for a long time.
(2) RTL Compiler, including the option to leverage physically-aware synthesis, in order to get the best optimizations for the ECO logic.
(3) Encounter Digital Implementation System (EDI), to merge the ECO changes into the design in the physical world, as Cadence's leading edge back-end design tool.
With all these strong technologies working hand-in-hand, I am excited and look forward to hear many customer successes in the near future.
If you have any comments based on your experiences with ECOs in the past and present, or have any questions regarding ECOs, I would appreciate hearing from you.
Good luck with your meeting your digital end-to-end needs with the best ECO methodology and underlying technologies. See you at the finish line!
Kenneth Chang, Product Manager