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We are often asked, by engineers doing synthesis, "Does Encounter® RTL Compiler support ILM(s) - Interface Logic Model(s) during synthesis? How to use ILM? What are its benefits?"
In this blog, I will not only provide some basic information about ILMs, but also point readers to a learn-by-doing content on RC Hierarchical ILM flow packaged in a RAK (Rapid Adoption Kit).
Interface Logic Model (ILM) is a technique to model blocks in hierarchal VLSI implementation flows. The advantage of the abstracted ILM approach is that entire path (clock to clock path) is visible at top level for interface nets unlike traditional block based hierarchal implementation flow. That gives better accuracy in analysis for interface nets at negligible additional memory and runtime overhead.
There is no specific requirement for ILM models. You would generate an ILM model for your implemented block, in Encounter® Digital Implementation or Encounter® RTL Compiler. The requirement will change at top level in terms of constraints. You will need to read your top-level constraints which include references to block as well. So you will need full top-level constraints so that exceptions like false-paths between top and block etc. are correctly applied.
Here is the simple version of using ILM at top level:
read_ilm -basename <path of ILM of other blocks> -module <>
assemble_design # This will load data for ILMs
<TOP level constraints and setup>
Write_design -hierarchical -encounter
Also, in today's high utilization designs, following steps are essential:
Benefits of ILM:
In general, Interface logic contains all the circuitry leading from I/O ports to edge-triggered registers called interface registers. The clock tree leading to interface registers is maintained as it is in ILM. Logic/circuitry that only consists of register-to-register paths on a block is not a part of an ILM.
The SI ILM logic model, also known as XILM, contains logic and capacitance information to model SI effects on interface timing.
Keeping this in mind, Shreyash Shukla, Principal PE, Synthesis R&D, Cadence Design Systems has developed a new RAK on RTL Compiler: Hierarchical ILM (Interface Logic Model) Flow, that will help user walk through the complete Hierarchical ILM flow available in RC, including generating ILM from RC and assemble design flow for ILM blocks.
Rapid Adoption Kits
RTL Compiler: Hierarchical ILM (Interface Logic Model) Flow
Download (48 MB)
10 Dec, 2013
We are covering the following technologies through our RAKs at this moment:
Synthesis, Test and Verification flow Encounter Digital Implementation (EDI) System and Sign-off Flow Virtuoso Custom IC and Sign-off Flow Silicon-Package-Board Design Verification IP SOC and IP level Functional Verification System level verification and validation with Palladium XP
Please visit http://support.cadence.com/raks to download any RAKs of interest.
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Note: To access above docs, click a link and use your Cadence credentials to logon to the Cadence Online Support http://support.cadence.com website.