Get email delivery of the Cadence blog featured here
If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage
you to check out Richard Goering's writeup on the new era of SoC design being
driven by applications.
It describes how Gadi Singer of Intel discussed new TVs that are networked
and can run apps on them (which for me is much more exciting than 3D). And Gadi
was followed by Cadence's John Bruggeman, who connected this to the EDA360
vision and described some of what is required to make this happen.
What jumped out at me in John's part was that all of these high-level design
concepts need to be connected to implementation. We have heard a lot about the exploration,
productivity, and re-use benefits of high-level design, but how do you connect
that to the existing silicon realization methodologies? The answer lies with
In this new era of SoC design, a top-down approach that considers the
architecture and partitioning of software, firmware, and hardware is essential.
The next steps in today's methodologies would have these teams all head off in
different directions and reunite a year down the road to see if everything
works together. Of course, we need to move to a methodology where the
development of these areas is done together for as long as possible, to
identify issues and make changes as early as possible. The way to accomplish
this is to describe the hardware at a high-level to figure out the best algorithms
for your overall performance, power, and cost goals. SystemC of course was
designed for this. And this is the point where logic designers come in.
Logic designers have the most experience in balancing these orthogonal goals
in hardware, and they understand what is possible in a given process
technology. Essentially they are the bridge between the system and the silicon.
They can help come up with the algorithms, then begin to flesh out the
functionality into a TLM description that can be used to functionally verify
the hardware. And this is where the connection to today's mainstream flows
TLM synthesis has been around for a number of years. Cadence's C-to-Silicon
Compiler, however, is the first high-level synthesis tool to actually connect to
implementation. It does this by using RTL Compiler synthesis inside to get an
accurate picture of performance, power, and area for its options as it's making
tradeoffs under-the-hood. This is extremely important, so that the resulting
RTL will synthesize without surprises.
And like RTL synthesis, TLM synthesis is not a push-button process -- it requires
design knowledge. For instance, specifying how many pipeline stages is
reasonable for meeting your throughput goals. Or which blocks of logic you
should push the performance, or the power, or the area. Even which
power-savings techniques should be used. And of course these blocks of
generated RTL will need to be integrated with re-used and externally-produced
So moving design to a higher level does not reduce the role of logic
designers -- it just changes it. It lets logic designers focus on bigger-picture
problems, leveraging their expertise to make a bigger impact on the success of
the end-product. Ultimately the logic designer will be less focused on squeezing
picoseconds out of register-to-register timing paths and more focused on
implementing algorithms in the context of the goals of the SoC. But in order to
make this leap to enable the next era of SoC design, logic design expertise
will be crucial.