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Quality of Silicon improvements. A lot of work continues to go
into improving results, especially physical results. We have seen some early-adopter
partners gain some significant area, timing, and power savings (these tend to
be design-dependent and constraint-dependent, of course).
Multi-vt algorithm improvements.
We have done a lot of work in the multi-vt engine to deliver the best balance
of all your design goals. With 10.1.100, the low-effort multi-vt setting will
now focus on minimizing leakage power with no area penalty. Medium and high
efforts will still prioritize leakage optimization over area, and these effort
levels have seen reductions in leakage power versus previous releases. And the default
multi-vt effort setting is now medium-effort.
Runtime improvements for large
designs. This continues to be a focus area for the team, as the size of
designs being synthesized is growing. RC comfortably turns around 1M instances (that's
3-4M gates) overnight, and we are looking to speed things up even more for 1M+
Floorplan tweaking. When you
identify an issue in RC-Physical that is floorplan-related, wouldn't it be nice
to be able to try tweaking something in the floorplan yourself to see if it helps?
This should help speed up resolution of these types of issues, since you don't
have to bother the physical design team and wait for them to get a chance to
make the change.
Rapid re-synthesis. This is a new
capability in RC-GXL that speeds up turnaround time when trying different
things on the same design. So after you synthesize a design and want to change
a constraint, or attribute, or RTL; as long as the change is fairly localized,
the turnaround time will be much shorter than a full re-synthesis.
Superthreading no longer requires
GXL. Again on the faster turnaround theme, we want everybody running RC as
fast as possible! So superthreading no longer requires an RC-GXL key to enable
DFT. We have done a lot of work over the past 18 months to make test logic insertion work seamlessly within synthesis. Now that we feel it is
well-integrated, we are starting to build out the feature set some more. This
release features improved power estimation of test logic with the "report_test_power"
command. It also adds the ability to insert asymmetric compression logic to
reduce pin count in compression mode. And finally you can insert MBIST that can
be accessed directly without having to go through the TAP.
Those are the major items -- there are a lot of smaller improvements as well.
And we have more planned for the second half of the year, so stay tuned. We
will be doing update training throughout the second half of the year, so please
contact your local Cadence synthesis expert for details or input/feedback on
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