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I am passionate about
synthesis. Almost 20 years ago I began using Synopsys "Logic
Compiler" to do combinational synthesis and optimization from Verilog RTL.
At that time it did not support sequential constructs so Flip-Flops had to be
manually instantiated in the netlist.
Synthesis has matured and
advanced considerably in the past couple of decades to the point where even
hardcore custom designers are migrating more and more logic to automated tools.
Until recently, synthesis
tools relied on algorithms developed at Berkeley
labs in the late 80's. High level Boolean optimization (remember Karnaugh
maps?) was done to reduce the number of logic levels, equation terms, etc. This
works well for reducing area, however, it is not done in a timing-aware context
and therefore may not give the best starting point for timing optimization.
Some synthesis tools still rely on this today.
Cadence Encounter RTL
Compiler (RC), however, uses a different approach to high level optimization
called "Global Synthesis". High level optimization (before mapping to
technology gates) is done in a timing, power, area and physically-aware
context. RC pre-analyzes the technology and physical libraries to determine
typical gate and wiring delays for the target technology of the device. Global
Synthesis does high-level optimization such as structuring, resource sharing,
speculation, etc. fully aware of timing and physical properties, with power,
area, and yield as cost functions. This gives a much better starting point for
technology mapping and optimization, which results in a better netlist for
place and route.
So, next time you execute
the "synthesize" command in RC, remember, its not just synthesis as
usual, its science!
For more information, we
have a white paper..
Also, you can check
out our global synthesis patents, they are 6,470,486 and 6,516,453