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  • Jack Erickson
    When Will We Move From RTL to TLM? I Need to Know!
    By Jack Erickson | 8 Mar 2010
    My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference...
    0 Comments
    Tags:
    TLM | RTL | Logic Design | rtl compiler | C-to-Silicon | Synthesis
  • Jack Erickson
    What Can We Learn From The iPad About Chip Design?
    By Jack Erickson | 2 Feb 2010
    You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT...
    0 Comments
    Tags:
    Apple | IP | Jack Erickson | Imagination | Logic Design | system design | software | iPad | ARM
  • Jack Erickson
    RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!
    By Jack Erickson | 25 Jan 2010
    I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize...
    0 Comments
    Tags:
    TLM | timing constraints | Logic Design | rtl compiler | C-to-Silicon | Synthesis | Physical Synthesis
  • Jack Erickson
    My Wish List For The New Decade
    By Jack Erickson | 29 Dec 2009
    Okay, it's the holiday season and end of the year, so I'll combine it all and make a wish list for the new year (as it relates to chip design). Heck, it's the end of the decade - so why not make a wish list for the new decade? A decade...
    0 Comments
    Tags:
    4G | methodology | Santa Claus | EDA | Logic Design | metrics
  • Kenneth Chang
    Wrapping Up 2009 With Some Reflections
    By Kenneth Chang | 23 Dec 2009
    As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of...
    0 Comments
    Tags:
    ECO | ASIC | Low Power | 2009 reflections | logic design | C-to-Silicon
  • Jack Erickson
    Attention RTL Compiler Customers! RC 9.1.200 Is Here
    By Jack Erickson | 15 Dec 2009
    Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly...
    0 Comments
    Tags:
    runtime | RTL Compiler 9.1 | leakage power | synthesis methodology logic design conformal lec aborts | multi-vt | OPCG | Logic Design | QoS | clock gating
  • Jack Erickson
    Innovation != Invention
    By Jack Erickson | 3 Nov 2009
    There's a common misperception, especially in technology fields, that invention and innovation are interchangeable terms. Innovation is a new solution to a problem, a new way of doing things, something that creates new markets and categories. Yes,...
    0 Comments
    Tags:
    Apple | Jack Erickson | innovation | logic design | iPod
  • Jack Erickson
    How Much Power Are You Leaving On The Table?
    By Jack Erickson | 23 Oct 2009
    Everybody is looking to reduce their chip's power consumption these days. Often a lot of reduction is needed in order to fit in the desired power envelope. Until now, designers of chips for wireless applications formed the majority of the power management...
    0 Comments
    Tags:
    Jack Erickson | Logic Design | rtl compiler | Design Explorer | MSMV | Multi-Supply Multi-Voltage
  • Jack Erickson
    Physically-Aware Synthesis: This Time it’s Different
    By Jack Erickson | 16 Oct 2009
    RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that...
    0 Comments
    Tags:
    Physical timing closure | Jack Erickson | RC-Physical | Physical Prediction | Logic Design | rtl compiler | Physical Synthesis | ple physical global
  • Team FED
    How-to Plans for ECOs - Advice From Experts
    By Team FED | 15 Oct 2009
    By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or,...
    0 Comments
    Tags:
    ECO | conformal | RTL | Logic Design
  • Jack Erickson
    SoC and remodeling cost estimation
    By Jack Erickson | 6 Oct 2009
    Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip...
    0 Comments
    Tags:
    chipestimate | Jack Erickson | logic design | spreadsheet | chip planning | chip estimate
  • Jack Erickson
    Branching Out - My Twitter Experiment
    By Jack Erickson | 5 Oct 2009
    I enjoy writing on this blog, but I don't get to post nearly as much as I would like. So I am going to try posting more often over on Twitter. It should be less-formal and more conversational, which are both more up my alley. I will of course continue...
    0 Comments
    Tags:
    Jack Erickson | Logic Design | Twitter
  • Jack Erickson
    How Do Logic Designers Become Rock Stars?
    By Jack Erickson | 22 Sep 2009
    Cadence's new Chief Marketing Officer, John Bruggeman just published a guest post over at one of my oft-read blogs, EDA Graffiti . In it he talks about Intel's "rock stars" - our logic design brethren - and how the model of relying on these rock stars...
    0 Comments
    Tags:
    Jack Erickson | logic design | EDA Graffiti | John Bruggeman | rock stars
  • jflieder
    The Current State of the Art for Physical Synthesis - A Response
    By jflieder | 14 Sep 2009
    I am posting this detailed blog in response to an article posted on John's Semi-Blog regarding the current state of physical synthesis tools. I too have been involved in this domain all the way back to the Links to Layout methodology of the mid to...
    1 Comments
    Tags:
    RC-Physical | Logic Design | rtl compiler | PLE | RC-Spatial | Physical Synthesis
  • Jack Erickson
    Friday Fun: Tapeout!
    By Jack Erickson | 11 Sep 2009
    Well, this is the finale of this season of The Next Generation. In it, the Dante Semi team celebrates their on-time tapeout, thanks to adopting modern design methodologies. It also has a bit of intrigue at the end. Hopefully this series has been entertaining...
    0 Comments
    Tags:
    friday fun | The Next Generation | Logic Design | Conformal ECO
  • Jack Erickson
    RTL Power Estimation
    By Jack Erickson | 8 Sep 2009
    RTL power estimation is a concept that has existed for a long time. The earlier that you can understand where power is consumed by your chip, the easier it is to make a positive impact. The challenge of course is obtaining accurate estimates. It is easy...
    0 Comments
    Tags:
    RTL power estimation | Jack Erickson | Logic Design | rtl compiler | low power design
  • Jack Erickson
    Friday Fun: A Last-minute ECO
    By Jack Erickson | 4 Sep 2009
    In this week's episode, the Dante Semi team is about to tape out when they get a last minute spec adjustment from their primary customer. Does this sound familiar? How will they make the change and verify it quickly enough to be able to tape out on...
    0 Comments
    Tags:
    ECO | C-ECO | friday fun | The Next Generation | Logic Design | caveman | Conformal ECO
  • Jack Erickson
    Friday Fun: Cutting Ties to the Past
    By Jack Erickson | 28 Aug 2009
    In last week's installment , we left the Dante Semiconductor team when they were nearing tapeout, but their old vendor was asserting its own interests over that of the project. In this week's episode, the team comes together to break the final link...
    0 Comments
    Tags:
    Static timing analysis | friday fun | The Next Generation | Logic Design
  • Jack Erickson
    Friday Fun: Adopting New Low-power Design Techniques
    By Jack Erickson | 21 Aug 2009
    This week's episode has the Dante Semi team employing some new low power design techniques, and using Conformal Low Power to verify their implementation of them. You will also see how the verification team uses low power simulation with Incisive to...
    0 Comments
    Tags:
    logic | friday fun | Conformal Low Power | Incisive | The Next Generation | design | low power design
  • Jack Erickson
    Friday Fun: Modern Methodology Has Benefits
    By Jack Erickson | 14 Aug 2009
    In this week's episode of "The Next Generation", the Dante Semi team reviews the project status after adopting many new techniques, such as power shutoff, assertion-based verification, physical synthesis, and multi-supply multi-voltage optimization....
    0 Comments
    Tags:
    friday fun | MSV | adult | The Next Generation | Logic Design | assertions | low power design | Power Shut-Off
  • Team FED
    Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
    By Team FED | 11 Aug 2009
    By Ankush Sood Principal Product Engineer Congestion is at the heart of the design closure challenge today. With smaller cell dimensions, increased chip-size and an inclination of design houses to reduce metal layers available for routing (to save...
    2 Comments
    Tags:
    Ankush Sood | RTL Compiler 9.1 | RC-Physical | congestion | Logic Design | Synthesis
  • Kenneth Chang
    I Need ASIC IP. Where Can I Find Information?
    By Kenneth Chang | 7 Aug 2009
    By Kenneth Chang. The world's best IP ecosystem is ChipEstimate.com . That's what we're hearing every day from our customers. Second to none as a solution, ChipEstimate.com took DAC by storm, with its incredible line up of IP Talks! sessions with...
    0 Comments
    Tags:
    DAC | ASIC | IP | Logic Design
  • Jack Erickson
    Friday Fun: The Next Generation is Back!
    By Jack Erickson | 7 Aug 2009
    After a bit of a hiatus due to some production issues, we're resuming the series of The Next Generation episodes. This week's episode starts with a review of the previous episode since it was so long ago, and deals with how companies have to make...
    0 Comments
    Tags:
    friday fun | EDA | Logic Design
  • Team FED
    Do You Also Need to be a DFT, STA, Verification, Low-Power, and Library Expert? Not Anymore!
    By Team FED | 4 Aug 2009
    By Jack Marshall Sr. Tech Leader, Solutions Our R&D team has just released a major new feature in RTL Compiler 9.1.100. It is called "Quality Analyzer". I call it "RC QA" for short - since that's how you invoke the feature (rc -qa)....
    0 Comments
    Tags:
    conformal | DFT | Low Power | SDC constraints | cadence | Jack Marshall | Logic Design | rtl compiler
  • Team FED
    RTL Compiler's New "Spatial Technology"
    By Team FED | 28 Jul 2009
    By Jeff Flieder Sr. Solutions Manager Over the last few years, RTL Compiler has added a significant number of features targeted toward users that require more physical awareness in their synthesis flow. We first introduced the PLE (Physical Layout...
    2 Comments
    Tags:
    Spatial | RTL Compiler 9.1 | Jeff Flieder | Physical Prediction | Logic Design | PLE
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