<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>How Is the Semiconductor Industry Handling Scaling: Is Moore&amp;#39;s Law Still Alive?</title><link>/cadence_blogs_8/b/life-at-cadence/posts/soc-demands-is-moore-s-law-still-alive</link><description>The chip design industry is going through exciting times. Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. This reduction in the process nodes has been predicted</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>