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  • TheLowRoad
    The Power of Big Iron
    By TheLowRoad | 11 Nov 2014
    Key findings: 5X to 32X faster low-power verification using Palladium XP emulation It’s hot in July in Korea, and not just the temperature; the ideas, too. The ideas that flowed at CDNLive Korea were exciting, and that includes a very interesting talk by Jiyeon Park from the System LSI division of Samsung Electronics. His talk, titled “Enabling Low-Power Verification using Cadence Palladium XP,” struck a chord with...
    0 Comments
    Tags:
    Low Power | Power Shutdown | Samsung | low power verification | Emulation
  • Adam Sherilog
    Freescale Success Stepping Up to Low-Power Verification - Video
    By Adam Sherilog | 17 Jan 2014
    Freescale was a successful Incisive ® simulation CPF low-power user when they decided to step up their game. In November 2013, at CDNLive India, they presented a paper explaining how they improved their ability to find power-related bugs using a more sophisticated verification flow. We were able to catch up with Abhinav Nawal just after his presentation to capture this video explaining the key points in his paper. ...
    0 Comments
    Tags:
    simvision | CPF | Incisive Enterprise Simulator | Incisive Enterprise Manager | MDV | simulation | verification
  • Adam Sherilog
    ST Microelectronics Success with IEEE 1801 / UPF Incisive Simulation - Video
    By Adam Sherilog | 15 Jan 2014
    ST Microelectronics reported their success with IEEE 1801 / UPF low-power simulation using Incisive Enterprise Simulator at CDNLive India in November 2013. We were able to meet with Mohit Jain just after his presentation and recorded this video that explains the key points in his paper. With eight years of experience and pioneering technology in native low-power simulation, Mohit was able to apply Incisive Enterprise...
    0 Comments
    Tags:
    IEEE 1801 | simvision | Incisive Enterprise Simulator | UPF | simulation | verification
  • Adam Sherilog
    IEEE 1801/UPF Tutorial from Accellera—Watch and Learn
    By Adam Sherilog | 18 Dec 2013
    If you weren't able to attend the 2013 DVCon, you missed out on a great IEEE 1801/UPF tutorial delivered by members of the IEEE committee. Accellera had the event recorded and that recording is now posted on the Accellera.or g website. Regardless of your work so far with low power design and verification, you need to watch this video. Power management is becoming ubiquitous in our world. The popular aspect is that...
    0 Comments
    Tags:
    Low Power | IEEE 1801 | IEEE 1801-2013 | Accellera | UPF 2.1 | UPF
  • Adam Sherilog
    Low-Power IEEE 1801 / UPF Simulation Rapid Adoption Kit Now Available
    By Adam Sherilog | 21 Nov 2013
    There is no better way other than a self-help training kit -- (rapid adoption kit, or RAK) -- to demonstrate the Incisive Enterprise Simulator's IEEE 1801 / UPF low-power features and its usage. The features include: Unique SimVision debugging Patent-pending power supply network visualization and debugging Tcl extensions for LP debugging Support for Liberty file power description Standby mode support...
    0 Comments
    Tags:
    Low Power | IEEE 1801 | Functional Verification | Incisive Enterprise Simulator | IEEE 1801-2013 | IEEE 1801-2009 | RAK | Incisive | 1801 | UPF 2.1 | UPF | RAKs | simulation | IES
  • QiWang
    Mixed-signal and Low-power Demo -- Cadence Booth at DAC
    By QiWang | 31 May 2013
    DAC is right around the corner! On the demo floor at Cadence® Booth #2214, we will demonstrate how to use the Cadence mixed-signal and low-power solution to design, verify, and implement a microcontroller-based mixed-signal design. The demo design architecture is very similar to practical designs of many applications like power management ICs, automotive controllers, and the Internet of Things (IoT...
    0 Comments
    Tags:
    DAC | Low Power | microcontrollers | IBM | Palladium | Mixed Signal Verification | Incisive | mixed-signal low-power | encounter | Low Power Mixed Signal Verification | Virtuoso | Internet of Things | low-power design | mixed signal | GlobalFoundries | ARM | Design Automation Conference | microcontroller
  • QiWang
    Insider Story of the New IEEE 1801-2013 (UPF 2.1) Standard
    By QiWang | 31 May 2013
    The IEEE has announced the publication of the new 1801-2013 standard, also known as UPF 2.1, and immediate availability for free download through the IEEE 1801-2013 Get Program . Even though the standard is new to the whole world, for the people of the IEEE working group this standard is finally done and is in the past now. There is a Chinese saying "好事多磨" which means "good things take time to happen." I forgot the...
    0 Comments
    Tags:
    Low Power | IEEE 1801 | power format standards | CPF | IEEE 1801-2013 | Qi Wang | power intent | UPF 2.1 | UPF
  • Adam Sherilog
    New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
    By Adam Sherilog | 7 May 2013
    On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release. When we talk about low-power verification its easy to equate it with simulation. For certain, simulation is the heart...
    0 Comments
    Tags:
    CPF 2.0 | uvm | Low Power | IEEE 1801 | PSO | CDNLive | CPF | Incisive Enterprise Simulator | IEEE 1801-2009 | power shutoff | Incisive | Adam Sherer | dpa | low-power design | UPF | power | IES | verification
  • Pete Hardee
    Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
    By Pete Hardee | 12 Feb 2013
    I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here . In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired by Horst Diewald, chief architect of MSP430 TM microcontrollers at Texas Instruments, the group's line-up is an impressive...
    0 Comments
    Tags:
    Low Power | microcontrollers | ultra low power | benchmarking | benchmarks | EEMBC | ULP | mixed-signal low-power | low power benchmarks | Internet of Things | low-power design | ARM
  • SumeetAggarwal
    New Rapid Adoption Kit (RAK) Enables Productive Mixed-Signal, Low Power Structural Verification
    By SumeetAggarwal | 10 Dec 2012
    All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for their analog block automatically, and run it through Conformal Low Power (CLP) to perform a low power structural check. The power structure integrity of a mixed-signal...
    0 Comments
    Tags:
    COS | conformal | VSE | Virtuoso Schematic Editor | Low Power | clp | Conformal Low Power | Cadence Online Support | Mixed Signal Verification | mixed-signal low-power | Mixed-Signal | Virtuoso | Power Intent Export Assistant | PIEA | mixed signal | design CPF | CPF Macro Modelling | Digital Front-End Design
  • Pete Hardee
    Low-Power Technology Summit Proceedings Now Available
    By Pete Hardee | 5 Dec 2012
    On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit Proceedings archive, which just went live. We've put both video and PDF versions of the presentations there. Obviously...
    0 Comments
    Tags:
    Anis Jarrar | MVt | PSO | ground level shifter | Jan Rabaey | Kinetis | body bias | Luke Lang | physical IP | Freescale | power gating | Substrate bias | MSV | shutoff | back bias | low power summit | Qi Wang | power shutoff | Mixed-Signal | broadcom | Low Power Mixed Signal Verification | Hardee | low-power design | DVFS | mixed signal | multi-bit flops | ARM | Power Shut-Off | Berkeley Wireless Research Center | BWRC | power optimization | dynamic power | power domains | PoP | reverse bias
  • Pete Hardee
    Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS
    By Pete Hardee | 29 Nov 2012
    The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises. First, some of the expected stuff. We'd noticed in the last major surveys done almost two years ago (see the Perspective on Power blog from December 2010) that advanced...
    0 Comments
    Tags:
    MVt | PSO | MSV | voltage domains | low power summit | encounter | supply voltages | Hardee | low-power design | DVFS | Advanced Features | low power survey | power domains
  • Pete Hardee
    Packed House Expected for Cadence Low-Power Technology Summit
    By Pete Hardee | 16 Oct 2012
    It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I'm expecting a great day -- we have a full agenda covering multiple aspects of low-power design. No longer the sole preserve of designers needing to extend battery life, low-power design has become ubiquitous in...
    0 Comments
    Tags:
    Jan Rabaey | physical IP | Freescale | low power summit | Mixed-Signal | broadcom | mixed signal | ARM | Berkeley Wireless Research Center | BWRC | PoP
  • Adam Sherilog
    Your First Low-power Verification Project - Webinar
    By Adam Sherilog | 11 Oct 2012
    So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls, isolation, and retention. As a verification engineer, you know that any test could trigger a power change either intentionally or in error. How do you build your environment...
    0 Comments
    Tags:
    IEEE 1801 | PSO | Functional Verification | CPF | Low-Power | power shutoff | webinar | UPF | IES
  • Pete Hardee
    Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year
    By Pete Hardee | 17 Sep 2012
    CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far from San Jose, USA; Munich, Germany; and Hsinchu, Taiwan. If you click on those proceedings links, you get to a multitude...
    0 Comments
    Tags:
    CDN Live | Low Power | Anis Jarrar | MVt | CDNLive | Kinetis | Sorin Dobre | Freescale | 28nm | CPF | Palladium | MSV | Conformal Low Power | Low-Power | encounter | Low Power Mixed Signal Verification | advanced verification | Qualcomm | low-power design | Power Analysis | CDNLive! | CPF Macro Modelling | Power Shut-Off | Common Power Format
  • SumeetAggarwal
    RAK: Conformal Low Power Advanced Features for Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling
    By SumeetAggarwal | 10 Aug 2012
    Why do you define macro models? Luke Lang , Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro without any low power component should be black-boxed. A macro model is not necessary." Luke further elaborates: "Custom IP blocks and analog macros often contain low-power features. A pure black box makes verification and...
    0 Comments
    Tags:
    Common Power Format 1.0 | Low Power | Functional Verification | CPF | Conformal Low Power | RAK | Low Power Mixed Signal Verification | low-power design | Advanced Features | CPF Macro Modelling | Rapid Adoption Kits | Power Intent Comparison | RAKs | Online Support | Hierarchical Integration | Digital Front-End Design | Cadence support | Formal verification | macro models
  • Pete Hardee
    Mixed Signals from European Low-Power Designers
    By Pete Hardee | 25 Jul 2012
    Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it a good time to visit - while it was nice in Germany the Northern European summer has been a disappointment so far, although the two days I spent in Scotland were, I'm told,...
    0 Comments
    Tags:
    Low Power | Europe | European designers | power gating | MSV | Low-Power | power shutoff | Mixed-Signal | moore's law | DVFS | mixed signal | wreal | Common Power Format | dynamic power | reliability
  • Pete Hardee
    What’s Cool for Low-Power at DAC?
    By Pete Hardee | 30 May 2012
    Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's booth #1930. Here is a quick guide to presentations, demos and other events Cadence is involved with for low-power, as well as the...
    0 Comments
    Tags:
    CPF 2.0 | DAC | Low Power | PSO | CPF | power gating | Low-Power | power shutoff | power-aware | Mixed-Signal | low-power design | UPF | Power Analysis | mixed signal | Power Shut-Off | power | Design Automation Conference | Common Power Format
  • Pete Hardee
    Low-Power Design? Brian Bailey Gets It
    By Pete Hardee | 2 May 2012
    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he put it: "I doubt if the EDA Designline, or in fact any Designline in the history of EE Times has ever had anything close to the...
    2 Comments
    Tags:
    Low Power | IEEE 1801 | MVt | PSO | PDN | EDA Designline | Luke Lang | energy harvesting | CPF | power gating | MSV | Low-Power | Qi Wang | power shutoff | Mixed-Signal | Power Delivery Network | Hardee | low-power design | UPF | mixed signal | Brian Bailey | Power Shut-Off | power optimization | Common Power Format | EE Times
  • Adam Sherilog
    Where There's Smoke, There's fire in the Belly of an Aspiring Engineer
    By Adam Sherilog | 2 Apr 2012
    Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current generation? Have apps deadened the EE in the way video killed the radio star? I am happy to report that the answer, for one future EEs at least, is a resounding "power up!" For some strange reason, my oldest son thinks EE...
    1 Comments
    Tags:
    EEs | Low Power | rocket sled | Ubuntu | advanced verification | smoke
  • QiWang
    CDNLive! -- The Other Side of the Low Power Design Techniques
    By QiWang | 29 Mar 2012
    In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with state retention, dynamic voltage frequency scaling (DVFS), body biasing, and multi-bit flip-flops. Even though each technique...
    0 Comments
    Tags:
    CDN Live | Annis Jarrar | Low Power | CDNLive | ground level shifter | Kinetis | Freescale | power gating | back bias | charge pump | CDNLive! | multi-bit flops | power optimization
  • Adam Sherilog
    Assertions Help Avoid Chip Melt
    By Adam Sherilog | 22 Mar 2012
    When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “ Avoiding Chip Melt ” article! Assertions are just the tip of the low-power verification iceberg. (Yep: iceberg + low-power +melting chips = metaphorical mayhem!) Kidding aside, in the article, both Erich Marschner from Mentor and I cite the...
    0 Comments
    Tags:
    ABV | AVS | Ann Mutschler | Low-Power | assertions | simulation | IES | verification
  • Pete Hardee
    Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!
    By Pete Hardee | 7 Mar 2012
    CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems. This year's theme is Connect, Share and Inspire. There's a particularly strong...
    0 Comments
    Tags:
    Low Power | CDNLive | Sorin Dobre | body bias | CPF | MSV | Low-Power | power shutoff | Mixed-Signal | advanced verification | low-power design | CDNLive! | mixed signal | Power Shut-Off | Common Power Format
  • Pete Hardee
    Does Substrate Biasing Have a Future?
    By Pete Hardee | 6 Feb 2012
    At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive power reduction techniques being adopted more widely as many designs, and by no means only mobile designs, become increasingly power-sensitive. But while many advanced...
    0 Comments
    Tags:
    biasing | PSO | body bias | power gating | Substrate bias | Low-Power | encounter | low-power design | Power Shut-Off | library | reverse bias
  • QiWang
    What’s Next in Low Power?
    By QiWang | 24 Jan 2012
    Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate advanced low power design techniques. No matter whether you are using the Common Power Format (CPF) or Unified Power Format (UPF), the methodology is the same -...
    0 Comments
    Tags:
    uvm | Low Power | CPF | GUC | tapeouts | advanced verification | UPF | power
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