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This posting is part of a series of blogs on dynamic power
management in digital-centric mixed-signal verification environments. In this
post, I'll discuss open-loop and closed-loop voltage scaling.
In previous blogs, I covered some of the following topics:
Previous postings include:
Closed Loop Voltage Scaling
Dynamic Frequency and Voltage Scaling (DVFS) is used for
power savings during off-peak processing times, and as a protective measure to
DVFS is the most commonly used form of DVFS. Here, the operating voltage point
or nominal voltage is pre-determined for the target application and desired
operating frequency. The aim is to run the device at the lowest possible
voltage while achieving desired performance.
actual clock speed of the device is determined by the PVT (Process, operating
Voltage and junction Temperature) corners. The desired clock speed is achieved
by scaling the voltage to the desired clock frequency based on statistical data
for that process. The operating voltage point for each target frequency is
typically stored in look-up tables and used by the power controller to scale
voltage up and down as needed by the application, as shown in Figure 1.
Figure 1: Open-Loop Voltage Scaling
safety reasons, there are typically large margins assigned to the operating
voltage points for each target frequency in the look-up table for open-looped
voltage scaling. To achieve the maximum power saving, there is a need to scale
the voltages with a much finer granularity.
the actual operating speed also changes with junction temperature (PVT), there
is a constant need to scale voltage to reach the optimal power reduction. This
is achieved by introducing a feedback loop to the power controller which
indicates how fast or slow a device is actually running based on PVT
characteristics. As shown in Figure 2, this feedback loop is facilitated by a Hardware
Performance Monitor (HPM) that enables closed loop voltage scaling. This forms
the basis of closed-loop Adaptive Voltage Scaling (AVS), whereby voltage is
adaptively scaled to achieve the optimal operating speed.
Figure 2: Closed-Loop
Adaptive Voltage Scaling
A noisy battery voltage is supplied from the verification
environment and controlled by the test parameters and supplied to the two low
dropout regulators (LDOs):
The two LDOs independently regulate the supplied battery
voltage to supply nominal voltages to independent power domains. There are 5
predefined nominal voltages for each LDO, and the outputs are independently
scaled under control from the power controller
to supply the regulated voltage to each individual power domain.
In my next blog, I will provide more information about
simulating closed-loop voltage scaling on a target DUT.
Stay tuned for more...
But isn’t it true that the excessive power scaling (or even power gating) can cause noise problems particularly because of surge currents that might result because of multiple locations across the chip being driven with high supply voltage (or low supply voltage) or even being switched off/on at the same time.
Another priority Feedback loop can be initiated which checks the maximum rise and fall of system current requirement doesn’t exceed a certain limit?