Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
This posting is part of a series of blogs on dynamic power
management in digital-centric mixed-signal verification environments. In this
post, I'll discuss the simulation of closed-loop voltage scaling for adaptive
dynamic voltage and frequency scaling (DVFS).
My previous blogs covered some of the following topics:
1. Basics of dynamic power management 2. Very brief introduction to RNM (Real Number
Modeling) for efficient simulation of mixed signal SoCs
3. How to create a controlled voltage source using a
4. Closed-loop voltage scaling
Previous postings include:
Simulation of Closed Loop (Adaptive) Voltage scaling
In this example, there are dedicated LDOs: ldo_mcu and
ldo_dsp are modeled as wreal data types, supplying regulated voltage to two
seperate power domains. The operating voltages are defined in the wreal models
of the LDO and individually configured from the verification environment.
Voltage transitions are controlled by the power controller based on estimated
processing needs that are task dependent.
A noisy battery voltage is supplied from the verification
environment and controlled by the test parameters and supplied to the two LDOs.
The LDOs independently regulate the supplied battery voltage to supply nominal
voltages to each independent power domain. There are 5 predefined nominal
voltages for each LDO, and the outputs are independently scaled under control
from the power controller to supply the regulated voltage to each individual
Figure 1: Closed Loop
Voltage scaling is orchestrated by controlling the output of
the LDO to supply a targeted nominal voltage independently for each power
1 shows how closed-loop voltage scaling is performed on
the SoC. The power controller determines the voltage level at which each power
domain needs to operate, and then fine-tunes the supplied voltage based on
feedback from the hardware performance monitors (HPMs) to perform closed-loop
The HPMs are strategically placed inside the SoC and measure
the targeted performance for each design unit. They provide feedback to the
power controller to increase or decrease the operating voltage in real time.
These are also modeled using wreals. The delay parameters and update rates are
programmable and controlled from the verification environment.
The results of simulating adaptive voltage and frequency scaling
are illustrated in Figure
Figure 2: Adaptive Voltage and Frequency
In the next blog posting, I will write more about error
detection during voltage scaling.
Stay tuned for more...