Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover error detection.
My previous blogs covered some of the following topics:
1. Basics of dynamic power management2. Very brief introduction to RNM (Real Number Modeling) for efficient simulation of mixed signal SoCs3. How to create a controlled voltage source using a Specman testbench4. Closed-loop voltage scaling5. Simulation of closed-loop adaptive voltage scaling
Previous postings include:
Controlled voltage source error detection
You may have a situation where a tightly controlled voltage source is created in the testbench, and noise is injected in the form of IR drop, switching and other noise sources. The level of noise is carefully controlled as test stimulus.
A noisy voltage source such as a battery supply that varies over time, and also drifts with temperature and use, can be created as shown in Figure 1. Error conditions like low and dead battery need to detected and tracked as seen in Figure 1.
Figure 1: Controlled Voltage Source with error detection
Voltage scaling error detection
The fundamental task of any verification exercise is the detection of errors. In this example, randomly generated noise is injected into the regulated output of the LDOs to emulate the effects of switching noise and IR drop on voltage of each power domain. This results in glitches, some of which occur close to the transitions of the nominal voltages of a given power domain, thus causing faulty voltage transitions.
It is important to detect glitches larger than a specified size and duration. Checkers are put in place to detect these. Any time these conditions are violated, the entire power domain is corrupted, as shown in Figure 2.
Errors are also detected by creating mixed-signal assertions that track expected behavior across the digital/analog boundary.
In the next blog, I will talk about Analog coverage and metrics.
Stay tuned for more...