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This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover error detection.
My previous blogs covered some of the following topics:
1. Basics of dynamic power management2. Very brief introduction to RNM (Real Number Modeling) for efficient simulation of mixed signal SoCs3. How to create a controlled voltage source using a Specman testbench4. Closed-loop voltage scaling5. Simulation of closed-loop adaptive voltage scaling
Previous postings include:
Controlled voltage source error detection
You may have a situation where a tightly controlled voltage source is created in the testbench, and noise is injected in the form of IR drop, switching and other noise sources. The level of noise is carefully controlled as test stimulus.
A noisy voltage source such as a battery supply that varies over time, and also drifts with temperature and use, can be created as shown in Figure 1. Error conditions like low and dead battery need to detected and tracked as seen in Figure 1.
Figure 1: Controlled Voltage Source with error detection
Voltage scaling error detection
The fundamental task of any verification exercise is the detection of errors. In this example, randomly generated noise is injected into the regulated output of the LDOs to emulate the effects of switching noise and IR drop on voltage of each power domain. This results in glitches, some of which occur close to the transitions of the nominal voltages of a given power domain, thus causing faulty voltage transitions.
It is important to detect glitches larger than a specified size and duration. Checkers are put in place to detect these. Any time these conditions are violated, the entire power domain is corrupted, as shown in Figure 2.
Errors are also detected by creating mixed-signal assertions that track expected behavior across the digital/analog boundary.
In the next blog, I will talk about Analog coverage and metrics.
Stay tuned for more...