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How easy is it to switch off power?
"Honey, could you please make sure all the lights are off before going to bed?" Although I am always wondering why I have to be one to do this, I do not have too many complaints as it is a job of simply flipping a switch.
Low power designers wish that designing a chip with power shutoff could be as simple as flipping a switch! The idea of power shutoff in chip design is like having light switches in your house, but how to get the design job done, and do it right on the silicon, is a very challenging IC design problem.
The most challenging part of the power switch network design is the lack of a product-proven methodology, because this is a relatively new problem to most IC designers. There are many different ways to implement a power switch network along with many different design constraints, which are sometimes conflicting with each other, that a designer needs to consider.
In addition, the power switch network design needs to be addressed throughout the full physical design flow, including floorplanning, place and route, extraction, power and power integrity analysis. Figure 1 shows a simple diagram of a power delivery network with power shutoff control on chip, along with the parameters and constraints.
Figure 1. Power switch network parameters and constraints
The first thing a designer needs to consider is to choose which type of power switch cells to use as the building block. Some switch cells have internal buffers between the enable input pin and output pin, and some do not. The switch cell without internal buffers may impose some additional implementation challenges because always-on buffers are required when connecting multiple switch cells into a chain.
Some switch cells have one enable control and some have two enable controls. The ones with two enables provide a way to control the power switch network ramp up time and rush current at power up. This is achieved by carefully designing the cell so that internally, one enable pin is connected to a smaller switch, and the other enable pin is connected to a bigger switch.
To connect such cells into a switch chain, the enable pins connected to the smaller or weaker switch should be chained up first, before chaining the enable pins connected to the bigger or stronger switch. To power up the switch network, the smaller switches will be turned on first to slowly bring the supply network to the expected voltage level with the rush current under control. After that, the bigger switches will be turned on to have the circuit ready for normal operation when the IR drop must be managed.
The next thing a designer needs to worry about is how many power switches are needed for a target block. You cannot have too few of them, as it leads to long power ramp-up times. However, you do not want to have too many switches either, as the power switches consume lots of power. The optimal number of switches depends on many different design constraints such as leakage power, rush current, dynamic and static IR drop, and ramp-up time.
After determining how many power switches are to be used to implement the switch network, the designer needs to figure out an optimal topology to connect all switch cells together. There are two major types of topology. One is the ring style and the other is the column style. Like everything else in the world, each has its benefits and shortcomings.
The advantage of the ring style switch network is that it will have a minimal impact on the traditional physical implementation flow. The designer can even design the switch network and the block controlled by the switches in parallel because the switches are not placed in the standard cell region. The downside of this approach is mainly the potential high IR drop when the block under control is very big, or having irregular shapes with logic placed far away from the ring.
The opposite is true for the column style switch network, where the IR drop can be well controlled because the switch cells are placed in the standard cell area. Another advantage of this approach is that it has more freedom in terms of how the enable chains are connected. The biggest problem of this approach is that you have do your power planning carefully with the switch cell location considered, and make sure the placement and routing tools are able to place and route the normal logic and the switch cells optimally.
Last but not least is the final signoff analysis to make sure the implemented switch network meets with all the required specifications such as static and dynamic IR drop, power up time, rush current and some other power integrity related specifications.
Figure 2. Power switch network implementation flow in Encounter Digital Implementation System
Cadence EDIS (Encounter Digital Implementation System) offers a production proven methodology to help designers to design and implement the power switch networks for designs using the on-chip power shutoff technique. Figure 2 illustrates several key steps in this flow. We will have separate blogs to dive into more details of each step to help you understand the methodology and how you can benefit from it to improve the productivity of your
power switch network design.
Good description of power shutoff issues at the power grid level.
Of course, there are also issues at the logical level, in terms of interfacing cells (ensuring a deterministic output from a block whose power has been turned off) and state retention flip-flops.