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Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate advanced low power design techniques. No matter whether you are using the Common Power Format (CPF) or Unified Power Format (UPF), the methodology is the same -- it uses a power format file to capture the designers’ power intent to drive the RTL-to-GDSII flow. The recent announcement of 100+ low power design tape-outs from Global Unichip (GUC), along with many other customers who have successfully adopted the Cadence CPF enabled low power solution, indicates the maturity of the methodology in real designs. So, what’s next?
One trend I see is that the concept of low power design is starting to penetrate into every corner of the IC design community. Traditionally, only a handful of projects in a company, or a small group of implementation experts, needed to worry about low power designs. Nowadays, almost every new design start is low power, and every designer, no matter what functionality he or she designs or verifies, needs to understand low power requirements and do something about them. To facilitate such a transition, EDA companies and chip design companies need to collaborate on educating the design community for the new era of low power everywhere.
The recent release of the book Advanced Verification Topics is a good step forward to expand low power design concepts to core verification engineers. Verification experts applauded the release of UVM standard, but how to leverage the new standard for low power design verification is still new to most designers. The book includes a dedicated chapter on low-power verification, with an in-depth discussion on power-aware verification planning and how to configure a power-aware UVM environment.
By bringing together two hot design topics, advanced verification and low power, the book provides unique value for verification engineers who want to apply latest verification technology on complex low power designs. I am sure there will be more such education materials in the future to help the general design community embrace low power design concepts.