Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit Proceedings archive, which just went live.
We've put both video and PDF versions of the presentations there. Obviously the PDFs give you the quickest access to the material, but you'd be missing a lot to just grab those. Seeing and hearing the presenter in action is important, especially when one of the keynotes, entitled "The power wall - are we scaling it or is it just getting higher?", is delivered by a noted expert like Professor Jan Rabaey of the University of California at Berkeley. The videos also have the Q&A sessions at the end of each presentation -- there were lots of good questions, and good interaction. You do need a "Cadence Community" login to access those, so there will be a quick one-time registration for the login if you don't already have it.
Prof. Jan Rabaey presents at the Low Power Technology Summit
As well as the keynote from Professor Rabaey (which Richard Goering also covered in a blog here), there were also presentations from Sathya Subramanian of ARM on Low-Power Design with ARM® Physical IP and POPTM IP, and technical updates from the Cadence team.
My personal highlight from the day was the presentation by Anis Jarrar of Freescale. Anis talked about all the measures they took to meet the aggressive power specifications on the Kinetis family of chips. Kinetis has been highly successful for Freescale, and they really are using all the tricks in the book (and then a few that aren't) to minimize power on these designs. You can also find more about Kinetis here. As well as the usual techniques (clock-gating, multi-Vt, Multi-Supply Voltage, Power Shut-off) they were also an early user of multi-bit register mapping in RTL Compiler. Further, they found a novel way to apply body bias that avoided the need for that inefficient, tricky way to generate a negative bias supply -- the charge pump. The audience was very happy to learn more about Anis's experiences, and the Q&A session for this one was lively and informative.
Finally, the presenters were joined by representatives of Broadcom and Berkeley Wireless Research Center for a panel session moderated by Richard Goering. Panelists provided a great low-power design-related discussion. You can also read Richard's blog on that, for a summary.