Low Power Blogs

Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;} In last month's blog entry "An Expert's View on Power Formats and Methodology", I highlighted a recent interview by Ed Sperling with Sorin Dobre of Qualcomm, posted on the Low Power Engineering Community. Amongst other things, Sorin explained how Qualcomm takes advantage of the hierarchical methodology in the Common Power Format (CPF).

This month, my good friend and Cadence colleague, Luke Lang, penned his third entry in a series of methodology articles, Hierarchical LP Design 3 in his "Everything Low Power" blog in the same on-line community. When taken with the other two (Hierarchical LP Design and Hierarchical LP Design 2) the series adds up to a comprehensive tutorial on both the value and the "how to" of hierarchical methodology in a power format, and the tools that support the format.

Luke first covers how macro modeling can capture power intent for IP blocks. Then he describes the capability to express power intent top-down, which can set rules abstractly without worrying about the details of all the power domain crossings lower in the design hierarchy. In his third entry, he elaborates on the bottom-up approach, and the ability to integrate the same block, in multiple situations requiring different use of the block's internal power intent capabilities. Finally he describes how to use virtual ports and virtual power domains to simplify specification of rules for design objects that will later appear lower in the hierarchy, as the design implementation refines.

Not all these hierarchical capabilities are truly unique to CPF. In fact, there is hierarchy support in the IEEE 1801 standard for soft IP blocks, although it remains limited by Liberty in terms of the power intent that can be described for a macro IP block. Another big problem is the inclusion of Unified Power Format (UPF) 1.0 in 1801, which is still the subset of 1801 supported by most UPF-based low power tools, and has only limited and incomplete semantics in terms of hierarchy.

So for now, these hierarchical capabilities are unique to the Cadence CPF-enabled low power solution. However, with our participation in IEEE 1801 and Si2's contribution of the CPF Open Low Power Methodology to IEEE 1801, we're rapidly progressing towards making these capabilities available to those who favor UPF too.

Pete Hardee