Low Power Blogs

As the clock for the 48^th Design Automation Conference (DAC) ticks away, we at Cadence are scrambling to put the final touch-up on all our DAC activities. Even though my time is limited, I still would like to highlight the significance of two recent and seemingly unrelated events.

First is a post at Deepchip.com on some user experiences with the Cadence Encounter® RTL-Compiler synthesis tool. In this post, two anonymous customers talked about their experience using the Common Power Format (CPF) to drive Cadence tools, including Incisive® Enterprise Simulation for low power simulation, RTL Compiler for low power synthesis, Conformal® Low Power for verification, and Encounter Digital Implementation System for physical implementation, to do low power designs.

One customer said, "I would definitely use RTL Compiler and CPF for our next low power design." And the other customer said, "Thanks to CPF and the power-aware simulations, our power domains worked, too!"

Second is the recent Silicon Integration Initiative (Si2) press release on the Open Low-Power Methodology (OpenLPM) contribution to IEEE 1801. This is probably the biggest news on power formats for the past few years, and I will for sure come back on this. What I would like to highlight now is the success of CPF and CPF-enabled low power solutions at some prestigious companies such as Qualcomm, TI, IBM, ST and LSI.  

One particular advantage of CPF, highlighted by Dr. Karim Arabi of Qualcomm, is the CPF hierarchical methodology, Quoted in the press release, he said that "At Qualcomm, we have been using CPF and found that formal hierarchical design flow support, with both bottom-up and top-down capability, are critical to enable complex advanced low power designs."  

Both events discussed above offered proof points for the success of CPF-enabled Cadence Low Power Solution. The Cadence Low Power Solution has been in production since 2007. In addition to the classical suite of tools mentioned above, recently added technologies in the solution are Palladium® Dynamic Power Analysis with CPF-aware emulation and Virtuoso® CPF generation from schematics.  

To understand more about the Cadence Low Power Solution and its unique capabilities, come to Cadence DAC booth 2237. For a complete schedule of floor and suite demos, check out Cadence at DAC 2011. If you have an iPhone, you can also download the latest "Cadence in Action" DAC application from the AppStore. Navigate through the "Cadence Demos" Tab, and you will find all Low Power Solution suite demos for each day under "Scheduled Demos." Requesting a seat in these demos is just a click away.  

Qi Wang