Low Power Blogs

Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he put it: "I doubt if the EDA Designline, or in fact any Designline in the history of EE Times has ever had anything close to the concentration of design articles, opinions, book excerpts that I will be putting up this month - and all of them will be on the subject of power." And I agree.

Contributions have come predominantly from EDA, and from pretty much all the players with any kind of power analysis, verification or optimization offering. There's good stuff from a lot of different companies, but since this is a Cadence blog, I make no apologies for highlighting the Cadence content here.

• In his opinion piece What Comes After Power Formats, Qi Wang elaborates on future developments we may see after the current focus on design automation for today's advanced low-power techniques. He touches on system level and software, novel clock tree methods, mixed-signal designs especially digitally-assisted analog, future process technologies, and 3D-IC.
• Next up, Buda Leung and I wrote a detailed case study of power analysis in Building predictability into your low-power design flow. We looked at the power savings achieved with multi-supply voltage domains, power shut-off, and multi-voltage threshold techniques, showing that RTL power estimation gets you early feedback on the benefit of these techniques, and could get pretty good correlation to sign-off analysis provided you use realistic activity vectors. We deservedly credited Paul Weil, John Decker and Mickey Rodriguez for the design work they did that made the article possible.
• Another major design article came from Luke Lang, who contributed Hierarchical methods for power intent specification. This article takes a comprehensive look at power intent specification for hierarchical designs, giving an in-depth "how to" on both top-down and bottom-up techniques, and pointing out that real-world design of any complexity is invariably a combination of both. Somewhere in the EDA Designline series, you can find an article on hierarchy management in UPF. Compare the two, and see which one makes more sense to you for real design. Maybe you will see why we're putting a lot of effort into driving methodology convergence with IEEE 1801 with broad industry backing, which is more fully explained in another EE Times article, co-written by ARM, Cadence, Qualcomm and TI, called Power Intent Formats: Light at the End of the Tunnel?
• In Brian's editorial Power 107: Power Delivery Networks, Brad Griffin is quoted extolling the benefits of full chip-package-board PDN modeling solutions.
• Finally, in Brian's latest editorial Power 108: Powering forward, I make some future predictions for 3 years and 10 years out. It's always difficult to know how far out on a limb to go on that kind of question, but all I ask is that, before you ridicule my predictions, let's see yours! However, I did note with a chuckle that, out of a list of 7 items predicted by a competitor for 10 years out, I believe Cadence customers already benefit today from 6 of them, with the remaining one on the roadmap slated for a release considerably sooner than a decade! Brian quite rightly pointed out that, 10 years out, you have to think a little outside the box.

Pete Hardee