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We drew lively interest on the DAC floor with our low power
demo station, which was continuously busy especially on the free Monday. We
were showing a new demo explaining how advanced low power techniques
("advanced" means the kind of techniques you need a power intent format to
describe -- more on this later) tends to introduce two kinds of problems we see
people struggle with:
The demo neatly showed how a comprehensive Cadence solution,
in this case highlighting Incisive Enterprise Simulator, RTL Compiler,
Conformal Low Power and Encounter Power System, solves these twin issues. The demo sparked lively conversations with a good sample of San Diego and Southern California's rich
population of power-aware designers, as well as dedicated travelers from
Meanwhile, in the suites, I asked the attendees in each low
power session how many were already using a power intent format, either UPF
(Unified Power Format) or CPF (Common Power Format), as a gauge of who was
already using advanced low power techniques. Typically, about half the room
would put their hands up. This led to two further trends:
For those that didn't put their hands up, I confirmed
the trend that many designers not in the traditional mobile applications are
realizing that their next designs are likely to need advanced low power
techniques anyway, either because they are moving to latest process nodes where
leakage is an issue, or because they need to control the thermal profile for
cost and reliability reasons, in the face of increasing performance of their
In the Cadence Theater on Tuesday, one low-power related
presentation drew great interest - Sorin Dobre of Qualcomm presented his
thoughts on power formats entitled "Power Intent Methodology Convergence: A Case Study of Hierarchical Flow". Sorin is one of the engineers who would raise
his hand to using both CPF and UPF, and his presentation described the need for
methodology convergence for power intent formats, and especially the need to
extend IEEE 1801 (UPF 2.0) with CPF's hierarchy capabilities. Which is quite
fitting, since one week earlier, Si2 announced the
contribution of relevant parts of the CPF specification to IEEE 1801 with a
view to achieve exactly that.
On Wednesday, the final day for the exhibition floor, with
the agreement of Texas Instruments India, I presented a paper in the Cadence
Theater on their behalf, first presented at CDNLive!
India, detailing the work of Rakesh Hariharan, Prabhu Bhairi, and Nithin
Maiya, in using Palladium to speed up RTL power-aware verification by up to 1000x.
That also drew a sizable, engaged crowd.
In these busy three days, San Diego lived up to its
reputation as a hot-bed of advanced low power design. In forthcoming blogs,
look for further explanation of the need for, and issues with, methodology
convergence as we drive that issue forward with the standards groups.