Get email delivery of the Cadence blog featured here
In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with state retention, dynamic voltage frequency scaling (DVFS), body biasing, and multi-bit flip-flops. Even though each technique can contribute some degree of power savings, not everyone is aware of the challenges and risks associated with each technique. During the Q&A session of the presentation, Annis revealed some interesting back-door facts that can provide some insights into these challenges and risks.
When asked about the challenges about multi-bit flip-flops, Annis brought up the following point. Dual or quad flops will deliver some significant dynamic power savings on the clock tree -- however, the benefits are marginalized when the bits go beyond four, except for highly structured data path logic. The biggest challenge of this technique is in physical implementation where routing congestion may be introduced due to the large cells. Designers may find that more than 90% of the flops need to be implemented with multi-bit flops to achieve the best power and timing.
Back biasing is a simple idea but it certainly has its own challenges. You need some extra routing for the bias supplies, but they tend to be much easier than the traditional power grid design because they carry very small amounts of current. However, to generate negative voltages for the NMOS biasing, you need a charge pump on chip, which by itself is very expensive in terms of silicon area and power!
To avoid this, designers can use reverse bias at the ground connection of NMOS. However, the challenge of doing this is that it requires a ground level shifter, which calls for a new IP design and new methodology for level shifter insertion and checking. How many people ever think about the need for a ground level shifter?
Finally, Annis brought up the importance of new design methodologies for low power mixed-signal designs because of the increasing popularity of low power design techniques in mixed-signal designs. There was another interesting presentation covering this subject in CDNLive! and we will cover it in a future blog post.
Lesson learned? There is no free lunch! Before you decide to use a low power design technique, think twice about the associated challenges and overall costs in terms of power, performance and area. The above presentation will be available soon for CDNLive! attendees from the Cadence CDNLive! site.