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There is a good article in the August edition of Microlithography World that anyone involved in managing OPC or DFM may want to read. I may be a bit biased (I was one of the authors) but it is good......
Here's a link to the article. Fujitsu, Applied Materials and Cadence collaborated for this article to discuss the process we used to help Fujitsu create CD-SEM recipes. It was a great experience and our collaboration helps determine the effectiveness of OPC on their silicon. Our results showed using the Cadence technology reduces the time spent on the CD-SEM recipe creation process by a factor of 6× (1,200 minutes to 213 minutes).
I would be very interested in what people think about the article and how they create CD-SEM recipes. Feel free to comment below.
When you cannot get closure between what you design and what you actually build with that design - sizing, placement, materials properties - you expect massive systematic failures. Design rule compliance can no longer be taken for granted. Our design and manufacture have gone beyond design verification infrastructure required for predictable execution. Yield learning is a terrible way to start learning DR violations. Extensive CD-SEM based metrology in layouts on production wafers is the right thing to do, as long as you get relevant and accurate data on DR compliance. Yet, I would think that much more is needed to regain closure.