It was a sunny, Sunday afternoon in Anaheim (across from Disneyland). That combination of weather and entertainment didn't sway a group of 35 engineers from participating in the DFMC (Design for Manufacturability Coalition) Workshop at DAC 2010.

On the panel were:


Rhett Davis - N. Carolina State Univ.

Bob Pack - Grid Simulation Technology, Inc.

Wilbur Luo - Cadence Design Systems, Inc.

Qi-De Qian - IC Scope Research

I took the opportunity to present the challenges and need for tight DFM integration into the design process. The goal is to generate layout that is highly manufacturable while meeting schedule and performance/power/area requirements. This "correct by construction" approach has, up until now, been fairly elusive due to old software architectures and limitations in the performance of the analysis tools.

What has changed? The next generation of digital and custom implementation tools (like Encounter and Virtuoso) are architected for plug-in analysis components. With this type of plug-in, analysis can be performed incrementally with knowledge of design intent and design state. For example, why spend costly CPU cycles to re-check an area that hasn't been changed during an ECO?

On the analysis front, new techniques have been created to speed-up checking (in some cases by several orders of magnitude). An example is pattern matching. Take a look at the presentation from GLOBALFOUNDRIES (by Luigi Capodieci). Through a tight foundry/EDA/design partnership, GLOBALFOUNDRIES and Cadence co-invented a new methodology (DRC+)  to identify and fix litho problems that is 100x faster than traditional approaches. At 28nm there is a large increase in data volume and in proximity effects, so without new thinking at this node, it would be impossible to move litho hotspot prevention/detection/correction early into the design process.

Here are the papers presented at the workshop.

Wilbur Luo