Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Mobile, automotive, consumer and medical applications require the productive realization of large and complex mixed-signal systems in silicon, and they must be on time and within budget constraints. Process capabilities make it possible to implement analog and RF circuits in CMOS technology at advanced nodes, and to integrate analog and digital functionality at the system-on-chip (SoC) level. However, mixed-signal SoC design is not without challenges, including the functional and performance verification of complex designs, concurrent analog and digital block/IP physical implementation, analog-digital physical integration, and signoff.
To address these challenges, next-generation mixed-signal solutions must enable unified design intent, abstraction and convergence throughout the design flow. These three capabilities are requirements of Silicon Realization, which is part of the EDA360 vision.
Capturing, Communicating and Verifying Intent
Today's mixed-signal designs are realized through collaborations of multiple teams spread across the world, performing different design tasks. Disjoint design environments and informal communications among designers often result in loss of productivity due to data conversions, increased design iterations, and error-caused ECOs. For example, if a designer implementing a block misses an e-mail message from a top-level integrator telling him that a particular clock net needs to be shielded, just before tapeout (or even worse after) the team might find out that the design does not function at the specified frequency due to crosstalk, costing them valuable time and resources to fix.
To avoid this kind of problem, the flow needs to capture the design intent (such as a shielding requirement), share it across different design tasks and teams, and verify that it is met before taping out. In the Cadence mixed signal solution this is achieved by using the common OpenAccess database not only for the smooth exchange of design data, but also for conveying intent in the form of design constraints across analog and digital domains.
Mixed-signal chips are increasingly power sensitive, and low-power design methodologies have to be applied throughout the mixed-signal design flow. Low power techniques like multi-threshold voltage, multi-power domains and power shut-off are increasingly used for minimizing the power consumption of mixed-signal blocks. SoCs often contain many mixed-signal blocks, and verifying power intent for the full chip using simulation is practically impossible due to the size of circuits and number of modes that need to be verified.
In its mixed-signal solution offering, Cadence leverages the CPF (Common Power Format) to capture power intent for a mixed-signal block, and then abstracts it to a level suitable for much more efficient formal (static) full chip verification, using the industry de-facto power structural sign-off tool Conformal Low Power. This methodology is much more productive in capturing functional and electrical bugs without requiring test-benches, increases coverage in much shorter verification cycle, and helps avoid costly silicon re-spins.
Abstracting for Efficiency
Continuous advancements in simulation speed and capacity are absolutely necessary, but are not enough to address verification challenges for complex mixed-signal SoCs. We have seen from many publicly known examples (including some very recent ones) that bugs missed in verification can cost company tens and even hundreds millions of dollars.
Model-based, metric driven verification methodologies need to be extended to analog and mixed-signal verification to improve the verification quality and productivity. In addition, Cadence has enhanced support for real number models in Verilog-AMS to enable more efficient abstraction of analog and mixed-signal functionality for inclusion into full chip, digital-centric, metric driven verification without sacrificing performance.
A traditional black-box methodology with sequential design tasks is inadequate for advanced mixed-signal designs, and leads to numerous iterations with slow or no design closure. Design convergence starts with the right chip architecture and optimal floorplan in terms of performance, area, power, noise and package cost. This can only be achieved through close collaboration among analog, digital and package designers.
The Cadence mixed-signal solution offers advanced chip floorplanning capabilities to facilitate cross-domain collaboration, enabling designers to explore different alternatives and choose the one with the best path to design closure. For example, designers can tune the initial floorplan using automated timing and congestion driven criteria while keeping sensitive analog objects at pre-set locations, quickly estimate and adjust the area for a block, and optimize pin locations of a block by considering both block and top-level routing requirements.
Integrated signoff analysis is another critical element for design convergence. Cadence offers advanced timing signoff analysis for the mixed-signal SoCs, breaking the limitation of the traditional black-box (.lib) model. The new methodology traverses the hierarchy of mixed-signal blocks and performs timing and SI analysis on critical paths spanning through top level and multiple mixed-signal blocks. Fully automated and joined with user-friendly debug capabilities, this enables designers to converge on the design spec and achieve fast, silicon correlated signoff.
By unifying mixed-signal methodology around design intent, abstraction and convergence, the Cadence solution increases design productivity and predictability and addresses mixed-signal SoC design challenges, enabling customers to improve profitability and competitiveness in the marketplace.
Cadence outlined EDA360 industry vision with Silicon, SoC and System Realization as its three pillars. Mixed-signal is integral part of EDA360 and is at the core of Silicon Realization. The unified mixed-signal methodology is a practical example of transforming the vision into reality. Cadence is presenting details of the unified mixed-signal methodology and showing how it is implemented in our mixed-signal solution in full day seminars to be held at 15 locations around the world. A detailed agenda and event registration is available at https://www.cadence.com/cadence/events/Pages/event.aspx?eventid=502