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networking, storage, computing and FPGA applications have been moving
aggressively to advanced process nodes to take advantage of lower power
consumption, improved performance and area reduction. Today, most of these
applications integrate a significant amount of analog/mixed signal (AMS) or RF together
with digital circuits. Since AMS often occupies over 50% of the chip area,
applying traditional, conservative approaches when migrating to an advanced
node diminishes and possibly eliminates these benefits.
significant changes in physical effects and device performance, a simple
migration to next node is not practical. AMS circuits need to be optimized and
often completely redesigned to meet performance specs. This requires design
companies to have an AMS IP flow fully ready at the same time as, or even
earlier than, the digital flow in order to realize silicon at advanced process
of 561 predominantly analog and mixed-signal designers and CAD engineers from
over 150 companies, collected during Cadence worldwide Mixed-Signal Seminars in
March 2011, confirmed that 65nm has became mainstream for mixed-signal. The
survey also showed strong AMS design activity at 40 and 28nm.
1 - Analog/mixed-signal designers look to lower process nodes
Challenges of Advanced Process Nodes
AMS chips at advanced nodes increases some of existing challenges and brings
new challenges. The main challenges include parametric variation, device
reliability, layout dependent effects (LDE) and overall design productivity.
designers analyze the impact of parametric variations and use more robust
circuit topologies and statistical circuit optimization techniques to center
designs to meet specifications with acceptable yield. Advanced node analog
circuits increasingly require self-calibration to cope with increased parametric
variation and process drift. Self-calibration typically involves digital logic
implemented tightly with analog circuits, requiring a mixed-signal flow instead
of pure analog design flow.
advanced nodes, devices are more susceptible to effects like Time Dependent
Dielectric Breakdown (TDDB), Hot Carrier Aging (HCA) and Negative Bias
Temperature Instability (NBTI). Any of these can cause device failure, particularly
if over-voltage conditions persist over longer periods. Therefore it is very
important to identify devices with over-voltage conditions across all modes of
operation and perform reliability analysis early in the design phase.
Due to LDE, device current and threshold voltage vary
depending on the surrounding layout. This is mainly caused by well proximity
and stress effects, and variation could be 10% or even more. To avoid late
layout re-work and schedule delays, it is important to understand impact of LDE
on circuit performance, identify the most sensitive devices, and implement them
in silicon with special care keeping variation within acceptable tolerances.
challenges require a higher level of design automation to keep up design
productivity at advanced process nodes. Accurately predicting circuit
performance in pre-layout stages, analyzing sensitivity and identifying the
most critical devices, capturing design intent, communicating intent as a
constraint to layout designers, and giving designers the means to construct
layouts correctly are all becoming mandatory.
TSMC AMS Reference Flow
the AMS reference flow initiative, Cadence and TSMC are closely collaborating
in addressing challenges of AMS design for the 28nm process. As result of this
collaboration, AMS v1.0 was released last year, followed by AMS v2.0 released
earlier this month. AMS v2.0 adds key features including LDE-aware layout,
advanced Monte Carlo Analysis, device reliability analysis, Analog Base
Sub-circuits (ABS) optimization and Multi Technology Simulation (MTS) for
2 - Cadence track in TSMC AMS v2.0 Reference Flow
In AMS v2.0, the LDE
calculation engine is tightly integrated in the Virtuoso environment to provide
almost instantaneous feedback to layout designers on the quality of device
placement through comparison of Vth and Id_sat variations of the particular
device against specified constraints. The high yield estimation in Virtuoso-ADE
using the Worst-Case Distance (WCD) method is validated to estimate yield
within 1% accuracy, with 200 parameter samples as compared to a traditional
10,000 random sample analysis.
Spectre/APS set in the Virtuoso-ADE environment are used to detect over-voltage
conditions that can lead to device reliability problems. Circuit optimization
capabilities in Virtuoso-ADE-XGL are validated for retargeting a generic ABS
cell to a specific 28nm technology that meets given specifications.
Additionally, a flow with Allegro SiP Architect and Virtuoso AMS-Designer was
qualified for analysis of 3D-IC integration, leveraging ther Multi
Technology Simulation (MTS) supported by Spectre.
on TSMC AMS v1.0 foundation in AMS v2.0, Cadence has delivered another strong
set of capabilities for much more productive and predictable AMS design at
28nm. For further information on the TSMC AMS reference flow please contact me,
your TSMC or Cadence representative.