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This is the first of a series of blogs where we will add pieces to the story over time. This is an email conversation between Fred and Harry, two fictional mixed-signal designers, where Fred is adopting various modeling techniques to realize faster simulations while maintaining acceptable levels of accuracy. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster).
How Fred came to mixed signal behavioral modeling
Hi Harry, Oh man, tape-out is in five days, and the SPICE level simulation is only at 2.34ns. With today's computers simulator performance is simply too slow, darn Moore's law. CU Fred
Hi Harry, I called Cadence and they suggested APS (Virtuoso Accelerated Parallel Simulator). Wow, that made a difference. I can now burn a whole 16-core machine. It should be okay for this project, but we will need something faster moving forward.Bye, Fred
Hi Harry, Cadence said to look into modeling and DMS (Digital Mixed-signal) for the next project and finish this one with APS. It seems like a good idea for now. Wish me luck that I do not find any serious issues over the next few days.Cheers, Fred
Hi Harry, We did it. After some long nights, we finished verification just in time before the tape-out. Fancy a beer tonight?Let's hope the chip works. We did our best but who knows if this was good enough.See you tonight, Fred
Hi Harry, We are now on the next project. We need to do things differently this time. We really need to improve the verification coverage and speed up functional verification. There is no way that we can do this the same way as we have done before.
Talked with Cadence again and there will be a seminar tomorrow.I will keep you posted, Fred
Hi Harry, Cadence did a presentation on behavioral modeling. Here is my conclusion: There are various behavioral languages out there and it is critical to pick the right one for our problem. We ruled out all the VHDL flavors, as nobody here knows VHDL.
There is Verilog-A which is a pure analog subset of Verilog-AMS. This is mainly used for detailed analog models for performance type of verification. The language is quite simple but as noted by the Cadence guy, the devil is in the details, and it is not trivial to write a good behavioral model that provides the performance gains I need and also retains the right level of accuracy.
The advantage of the Verilog-A subset is that we can definitely reuse the models in pure analog simulations, like APS, as well as in our mixed signal environment. I will probably go ahead and suggest this language to our analog team, but for me this looks to low level. As said before, I need it really fast!!!
Then there is Verilog-AMS. As the name says, this is a superset of Verilog-A and Verilog-D. This language gives people a huge amount of flexibility. You can create all sorts of interactions between the analog and digital domains, and the simulator figures out in the background which solver to use. Man, this can get quite hairy. There were a few tricky examples in the labs.
One other takeaway point was "model what you need and not what you can." It took me a while to understand this but then the guy gave a few examples of folks creating highly accurate models that would model very tiny details of the analog behavior, while the purpose was only to verify the connectivity. Thus, all the modeling effort and the simulation performance were completely wasted.
Tomorrow should be interesting; we are talking about wreal modeling and Verilog-AMS.
Have a good day,