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Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is very hard to choose from so many options. Here is a quick guide to presentations, demos and other events Cadence is involved with for mixed-signal, as well as the latest updates on tools and flows support.
1. Tutorial on Analog and Mixed-Signal Design at Advanced Process Nodes (jointly by TSMC, Freescale, Cadence). Time: Monday June 4th 8:30 AM - 10:30 AM, repeated at 11:30 AM - 1:30 PM, and again at 3:30 PM - 5:30 PM. Location: 306 (Moscone Convention Center)
2. Luncheon on Overcoming Variability and Productivity Challenges in Your High-Performance, Advanced Node, Custom/Analog Design. Time: Monday June 4th 11:30AM - 1:00PM. Location: 270-276 (Moscone Convention Center)
3. Luncheon on Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs (jointly by ARM, NXP, Cadence). Time: Tuesday June 5th 11:30AM - 1:00PM. Location: 270-276 (Moscone Convention Center)
4. The pre-production release of the industry's first mixed-signal design methodology book, Mixed-Signal Design Methodology Guide. Time: Monday June 4th - Wednesday June 6th. Location: Cadence Booth #1930.
5. A demo on applying the latest mixed-signal verification methodology to a design using the Cortex-M0 in an ultra low power application. Time: Monday June 4th - Wednesday June 6th. Location: ARM Booth #1414, #802.
6. A floor demo of new tool capabilities to verify low power intent of a mixed-signal design from an analog design environment (Virtuoso) by leveraging digital tool capabilities (Conformal and Encounter). Location: Cadence Booth #1930.
7. Four exciting customer and partner presentations on mixed-signal design in the Cadence EDA360 Theater at Booth 1930:
8. Addressing Mixed-Signal Functional Verification Challenges using Virtuoso Multi-Mode Simulation. Time: Monday June 4th 12:00PM-1:00PM, Tuesday June 5th 2:00PM-3:00PM, Wednesday June 6th 9:00AM-10:00AM. Location: Cadence Demo Suite #2 at Booth 1930.
9. Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs. Time: Monday June 4th 3:00PM-4:00PM, Wednesday June 6th 4:00PM-5:00PM. Location: Cadence Demo Suite #2 & #3 at Booth 1930.
10. Boosting Productivity and Reducing Turnaround Time with an Integrated Mixed-Signal Physical Implementation Flow. Time: Tuesday June 5th 9:00AM-10:00AM, Wednesday June 6th 4:00PM-5:00PM. Location Cadence Demo Suite #2 at Booth 1930.
If you are still confused, there is only one way out - go to the Denali Party by Cadence. I wish everyone a fun time at DAC!