Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored by Pierluigi Daglio and Marco Carlini from STMicroelectronics that has garnered a lot of interest from the verification community.
Metric-driven verification is the norm for digital designs. But, we can extend this concept to analog/mixed signal designs. Analog/mixed signal verification in the context of full chip verification can achieve a respectable coverage level without compromising on performance levels of digital verification. This can be accomplished by using more robust and abstract analog behavior models such as Real Number (RNM) models using Verilog-AMS wreal as an example. RNM models are also provided in VHDL and System Verilog extensions as well.
Typically, analog verification is based on detailed transistor level simulations run using SPICE-level simulators in a bottom-up flow. Digital verification is based on a top-down approach and has a uniform verification plan using the Universal Verification Methodology (UVM). This metric driven approach uses coverage-directed random stimulus generation and supports multiple verification languages. However, with the trend towards complex mixed-signal SoCs, analog and digital verification cannot afford to stay isolated from one another.
To address the growing verification challenges in today's mixed signal designs, engineers have been using mixed-signal co-simulation. With this approach, the analog behavior models are modeled using Verilog-AMS or VHDL-AMS languages. Mixed-signal simulators are available to then simulate the analog portion using the analog solver and digital portion using a digital event driven simulation engine. But, this approach has 2 key disadvantages.
Newer approaches to using RNM to model continuous analog behavior in discrete digital models are gaining a lot of traction. The wreal language extension in Verilog-AMS offers the best trade-off between performance and accuracy, and thus helps analog designers achieve acceptable coverage levels. This performance gain is achieved by using fast digital simulators like Incisive Enterprise Simulator to replace extremely slow mixed-signal solutions.
In addition to performance gain, RNM models introduce a metric-driven verification approach as well as assertions to analog/ mixed-signal designs. With assertion-based verification, top-level verification coverage levels can be managed to the specifications as desired.
Cadence has further extended wreal beyond the Language Reference Manual limitations for more effective usage, and come up with flow that is unique and efficient. Apart from supporting wreal extensions in its verification offerings, Cadence is now pioneering key technologies that will make the use of RNM adoption easier for the verification teams.
Here are two new methodologies that are needed to accelerate the metric-driven verification approach for mixed signal designs:
A typical mixed-signal verification flow using RNM consists of the following:
To learn more about this topic, please see the following whitepapers:
Solutions for Mixed-Signal SoC Verification
Mixed-Signal Design Challenges and Requirements
You can listen to an audio recording of the STMicroelectronics EDA360 Theater presentation (June 5, 4:00 pm) and view the slides here.