Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees used the opportunity to ask questions, share experiences and network.
Dr. Chi-Ping Hsu, Cadence Senior Vice president of R&D, welcomed the participants and opened the event. He pointed to Cadence's strong investment and leadership in mixed-signal solutions.
Prof. Ali Niknejad of the University of California at Berkeley delivered an inspiring academic keynote "Pushing the Frontiers of Silicon: Digital RF, mm-Wave, and THz Communication and Imaging." He shared with the audience his research on RF circuit design and silicon implementation for energy efficient, wider bandwidth communication in the 60 GHz frequency range. In second part of his keynote, he discussed design challenges and techniques for silicon-based, reflection-sensing radar imaging, which could potentially replace today's expensive X-ray Computed Tomography (CT) scanners with much less costly solutions for medical imaging and diagnosis.
Chris Collins, Director of Analog EDA and Design Services at Texas Instruments delivered the industry keynote "Tribulations of Combining Analog and Digital Design." In a very entertaining way, Chris shared some of his experiences in deploying an advanced, productive and scalable flow for mixed-signal design. He stressed the importance of a close relationship and collaboration with Cadence for the success of his projects.
Dr. Monte Mar of Boeing Corp. talked about statistical behavioral modeling for sensitivity analysis of analog circuits in order to make feasibility tradeoffs, and choose more suitable circuit topologies and specifications for practical implementation in a top-down design methodology.
Frank Nothaft and Nishant Shah from Broadcom presented a methodology for validating and maintaining a portfolio of AMS IP behavioral models used in SoC verification. They particularly focused on a high level of automation for checking the equivalency of models with their corresponding circuits through efficient regressions.
Prashanth Aprameyan from Micron Technology focused on a comprehensive mixed-signal verification solution for NAND memory using SPICE/fast-SPICE simulation for verifying performance and IR drop impact, and complementing it with "wreal" type Real Number Modeling for full chip functional verification.
Tim Guglielmo and Subodh Reddy from Maxim Integrated shared their findings on the Schematic Model Generation (SMG) tool they evaluated in early partnership program with Cadence. The tool makes it easier for analog designers to create and verify behavioral models using a schematic environment, rather than writing them in a text editor.
Dinraj Shetty and Joaquin Bartra from Spansion talked about their physical implementation flow. Interoperable on OpenAccess, the flow enables analog and digital layout designers to share and refine floorplans with pre-routes done by a custom router which are honored by digital physical synthesis. Designers can easily take the design back to a custom platform for chip assembly.
Mahesh Tirupattur from Analog Bits, and Kumar Keshavan from Sigrity which is now part of Cadence, jointly presented on IBIS algorithmic modeling (IBIS-AMI) for effective channel simulation, applied to 10 Gbps SerDes.
Jim McCanny and Ben Farhat from Cadence discussed the increased importance of static timing analysis for mixed-signal designs, and presented a methodology for characterizing timing of custom circuits and full chip timing analysis using a glass-box (instead of black box) approach.
I had the pleasure of teaming up with Dominic Pajak from ARM to present on CortexTM-M processor benefits for mixed-signal applications, and simulation flow for hardware/software verification.
Presentations and videos from the summit are now available for viewing. Please visit http://www.cadence.com/cadence/events/Pages/Mixed_Signal_Technology_Summit_Proceedings.aspx, or click on the link for particular session of interest, below. A Cadence Community log-in is required - quick and free registration if you don't have one.