Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso Layout Suite, which provides a comprehensive set of routing features for a variety of layout tasks. One major design task for layout designs is chip/block assembly routing in mixed-signal analog top (AoT) designs.
What's new in Virtuoso IC6.1.6?
VSR routing engines were enhanced to improve routing quality (QoR) and to give better control over routing flow. You can run automatic routing using the Wire Assistant for improved usability. Now most of the functionality found in the Route --> Automatic Routing UI can be found on the enhanced Wire Assistant.
One of the benefits of using the Wire Assistant is that settings are consistent across all use models (Interactive Wire Editor, assisted routing, or automatic routing). Using the new Wire Assistant, users have control over pin access, via configuration, routing flow, and routing style/topology. Regarding topologies, the Wire Assistant adds support for these routing topologies:
In addition, the Wire Assistant has three pre-defined routing flows:
As in IC6.1.5, the Wire Assistant will dynamically populate sections in the UI to control any specific routing features.
Which technology nodes are supported?
VSR in Virtuoso IC6.1.6 supports design rules (constraints) for a broad range of technologies, from very mature "analog" nodes such as 0.25µm and 0.18µm, all the way to 22nm. In Virtuoso ICADV12.1, VSR supports advance routing rules for 20nm and below technologies, with support for double patterning (DPT) rules and interactive coloring.
If I need to add constraint, which routing constraints are supported?
VSR, as part of the VLS constraint-driven environment, supports specialty routing constraints such as bus, differential pairs, match length, symmetry, and shielding, as well as netClass and process-rule overrides (PROs, also known as non-default rules (NDRs)) for custom width and space and multi-cut via. It is also good to know that routing constraints are stored in OA, which makes them fully interpretable with EDI. So all routing constraints can be defined and edited in either VCM or in the EDI Constraints Editor to be used by the appropriate tools.
In my design, some of the macros have the abstract view and some do not. Do I have to generate abstracts for all my macro blocks?
No, but... Using some form of abstract will help to improve routing performance.
In order to simplify the use model, "Cover Obstructions" can be used for "on-the-fly" abstraction of macros (Cover Obstructions requires all pins to be placed on the prBoundary edge of the macro block). To use Cover Obstructions, go to Tools --> Cover Obstruction Manager.
When detailed abstracts are needed, as in cases when the use of the Abstract Generator is recommended for the control of routing porosity. To invoke, type "abstract" at the same location Virtuoso was invoked from.
What are the requirements for using VSR?
There are few things one should consider when using VSR automatic routing: The "cleaner" the layout data is, the easier it is for VSR to complete its tasks, which translates to higher quality of routing and better performance.
Here are few data requirements that should be checked prior to running automatic routing:
Why should I care about the signal type?
In IC6.1, unless specified otherwise, all nets are generated as type "Signal" and by default, VSR will route all nets of this type (Signal).
In order to differentiate the power and ground nets and force VSR to skip these nets during the automatic routing flow, users should specifically define these net types. To define nets to be of type Power or Ground:
Ready to route?
To route all nets, click the "All" button on the Wire Assistant "Automatic" section.
Or, select nets on the Navigator and click "Selected" on the Wire Assistant "Automatic" section to route only the selected set of nets.
Want to see VSR in action?
Navigate to support.cadence.com, look for Resources - Rapid Adoption Kits - Virtuoso Custom IC and Signoff and download a tarball to try out the new VSR or contact your Cadence account team for a live demo.