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A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled "TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design Infrastructure, Spanning Custom/Analog, Digital and Mixed-Signal Design." This press release emphasizes that TSMC's 20nm reference flow is not only for digital design using Encounter Digital Implementation (EDI), but is also for custom/analog design using Virtuoso, as well as sign-off using Encounter Timing System (ETS) and Physical Verification System (PVS).
This press release clearly validates Cadence's leadership in not just digital design, but also in analog design and more importantly the complex low-power mixed signal design that is prevalent in the marketplace. This is mainly due to the explosive growth of smartphones and intelligent electronic appliances. The majority of today's designs are true mixed -signal designs where there is an equal emphasis of analog and digital content in a single system-on-a-chip (SoC).
Cadence's "mixed-signal on top" Implementation solution is perfectly tuned to target these designs. Cadence's mixed-signal on top flow integrates the industry-leading Virtuoso platform for analog design, and the EDI platform for digital implementation, providing a seamless implementation methodology.
The second item that caught my attention is an ARM blog post titled 'Blurring the Analogue/Digital design frontier' written by Thomas Ensergueix, CPU Product Manager, ARM. He talks about an ARM-Cadence Cortex M0 Demo. This demo focuses on designing ARM's M0 based system based on the Cortex-M System Design Kit (CMSDK) using Cadence's mixed signal solution with an end to end implementation and verification flow.
On the implementation front, Thomas talks about the seamless integration of Virtuoso and EDI platforms through OpenAccess to tackle the true mixed-signal design featured in the Cortex M0 demo. The demo also features low power implementation and verification, which are natively supported using the Common Power Format (CPF). Finally, the simulation is done using the CPF-aware AMS Designer Simulator.
On the mixed-signal verification front, Cadence's Schematic Model Generation (SMG) and Analog/Mixed-Signal Design Model Validation flow (amsDmv) help analog designers bring verification into the digital domain. The blog also commends the Mixed-Signal ToT (Tech on Tour) that is offered around the world for its rich content and practical use cases.
Cadence is focused on providing scalable solutions for mixed-signal designs and has recently published the Mixed-Signal Methodology Guide written by industry experts from Cadence and other leading companies. If you're interested in learning more about Cortex M0 mixed-signal demo and Cadence mixed-signal solution offerings, please reach out to your Cadence representative. One of my earlier blogs also covers the ARM Cortex M0 based mixed-signal demo in detail.