Today Cadence's clipping service found a quote by Cadence in a press release by DFI Group, and when I first read about it, it was as if my brain stopped understanding what was clearly English. Sometimes working at this company is like that—Cadence’s tools and IP applies to so many obscure spheres of electronics, that sometimes I’ll come across something that makes no sense to this non-electronic engineer’s writer’s brain.

The headline on the press release was: “DFI Group Releases Initial Version of the DFI 5.0 Specification for High-Speed Memory Controller and PHY Interface.” Since a goal of mine is to try to get some understanding of what at least most press releases that involve Cadence are about, I figured it was time to do some research. Thank you to John MacLaren for your help!

So what are we talking about in this press release?

Background

Most chips have an interface to some external memory for data storage (memory). It is made of two pieces of IP: the memory controller and the PHY, or physical layer of the actual interface—the I/O buffers and analog pieces.

The memory controller is the “brains” of the logic of the chip that interfaces to the external memory. This is the digital portion of a chip, which handles timing, transactions, refreshes, and so forth—and is designed by digital designers.

The PHY is an abbreviation for the physical interface with the external DDR memory device. It defines the relationship between a device and a physical transmission medium, including the layout of pins, voltages, line impedance, wires, signal timing, and so forth. This is designed by analog designers and is specialized to the use of that memory component.

The problem is integrating these two domains. They are designed by completely different teams, and the IP may be from a third party or designed in-house or may be contracted out to a remote office outside of the country. But these two components need to be able to “talk” to each other.

About fifteen years ago, Denali (which was later acquired by Cadence) found themselves spending way too much time on this integration piece, which was custom for every customer. But Denali quickly came to realize that these integrations were really all the same, so they and a few other companies formed the DDR PHY Interface (DFI) committee to standardize this integration portion. The DFI committee now consists of eight IP vendors (including Cadence) and users (including Intel and Samsung). There are now over 3000 subscribers to this specification, so you can pretty much count on this being standard throughout the industry.

So the DDR PHY Interface (DFI) is the interface protocol that defines the connectivity between a DDR memory controller (MC) and a DDR physical interface (PHY) for DDR memory devices. The protocol defines the signals, signal relationships, and timing parameters required to transfer control information, read and write data to and from the DRAM devices over the DFI.

The press release is talking about the newest revision of this specification.

DFI 5.0

This is the seventh revision of the DFI specification.

In this revision, the following changes were made:

• Adds protocol support for the newest DDR (DDR5) and low-power memory technologies (LPDDR5). The two newest memory classes (remember, we’re talking about DRAM) are the fifth revision of double-data-rate (DDR5) and low-power double-data-rate (LPDDR5) memories. DDR5 reduces power consumption, while doubling bandwidth and capacity relative to DDR4 SDRAM, and is due to be released this summer. LPDDR5 is the newest generation of low-power memory used in mobile devices.
• Removed the “training” interface to PHY-independent training without involving the controller. Training refers to the way the signals are aligned within a chip. This previously was done by the controller and the PHY together across the interface; it is now handled independently with the PHY.
• Lower power enhancements. As with everything, low power is the key to the future of electronics, requiring special considerations in the interface.
• Providing a PHY-independent boot sequence.
• Expanding frequency change support.
• Defining new controller-to-PHY interface interactions.

Now that I have investigated this, at least I understand what the press release was about. New standards for the DDR-PHY interface, redefined for DDR5 and low-power DDR5, with a PHY-independent training portion and other improvements, have been announced by DFI. Just in time, too, since DDR5 will be released this summer, and Cadence has just announced the first IP interface in silicon for DDR5.

What is DDR5, you ask? Well, stay tuned for another blog post. I need to find out, exactly.

—Meera