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Featured

DesignCon 2025 Highlights and Papers on Demand

The Cadence MSA team had a GREAT DesignCon highlighting how Cadence can help you…

MSATeam
• 2 min read
featured , DesignCon , Advanced IC packaging , PCB design

Designing High-Performance Sensor Packages to Ensure Optimized Performance

In an era where technology and connectivity reign supreme, electronic, and mechanical…

Vinod Khera
• 4 min read
featured , IC Packaging , Allegro X Design Platform , EDA , MCAD-ECAD

Machine Learning Is Revolutionizing IBIS-AMI Optimization in High-Speed Design

The complexity of IBIS-AMI models used in simulating serial links has increased to…

MSATeam
• 1 min read
featured
System, PCB, & Package Design 
Latest blogs

What's Good About FPGA System Planner and Netgroups? 16.6 Has It!

Beginning with the 16.6 SPB release, FPGA System Planner (FSP) can create net groups…

• 2 min read
PCB , Cadence Design Systems , FPGA: ASIC Prototype , Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , FPGAs , PCB Editor , setup , Layout , Front-end PCB design , design , NetGroups , FSP , PCB design , Constraints , Grzenia , net groups , NetGroup , FPGA , FPGA Pin Assignment , FPGA: PCB

What's Good About DEHDL’s Variant Editor? 16.6 Has Several New Enhancements!

The recent 16.6 QISR-2 for Allegro Design Entry HDL has new capabilities for the…

• 1 min read
Cadence Design Systems , Allegro Design Entry , Allegro 16.6 , cadence , varient editor , 16.6 , SPB , design , Grzenia , ConceptHDL , Schematic , Allegro

Turn Spreadsheet Ball Maps into Components in Seconds with 16.6 Cadence APD and …

Many designers use ball maps, or spreadsheets wherein each cell corresponds to a…

• 5 min read
IC Packaging and SiP Design , SiP , IC Package , IC Packaging , packaging , spreadsheet , 16.6 , IC Packaging and SiP , IC package design , APD , IC Packaging & SiP design , BGA , Allegro Package Designer , ball maps , Allegro

What's Good About Allegro PCB Editor ECSets and Ref Des Values? 16.6 Has a Few New…

Beginning with the 16.6 Allegro PCB Editor , the environment variable UPDATE_ECSET_REFDES…

• 1 min read
PCB , Cadence Design Systems , Constraint-driven PCB Design flow , Allegro 16.6 , cadence , electronics design , 16.6 , SPB , PCB Editor , Constraint Manager , design , PCB design , Constraints , Grzenia , Allegro PCB Editor

What's Good About Allegro PCB Editor Embedded Net Name Display? Check Out 16.6!

A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within…

• 1 min read
PCB , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , Routing , 16.6 , SPB , PCB Editor , PCB routing , Layout , design , vias , "PCB design" , PCB design , Grzenia , pin planning , physical layout design , Allegro PCB Editor , color visibility , stipple , Allegro , etch shapes

Why Does Signal Integrity Analysis Need to be Power Aware?

Ever since the I/O Buffer Information Specification (IBIS) committee broke away from…

• 2 min read
IBIS Model , High Speed , Signal Integrity , power-aware SI , SI analysis and modeling , Allegro Sigrity

What's Good About AMS Simulator IBIS Model Capability? It’s in the 16.6 Release!

The 16.6 AMS Simulator now provides IBIS model simulation capability: SPICE circuit…

• 1 min read
PCB , Cadence Design Systems , AMS , Allegro 16.6 , cadence , AMS simulator , IBIS , 16.6 , Capture CIS , Capture-CIS , PSPICE , SPB , design , AMS simulation , Design Entry , Grzenia

Take Notes During Your Packaging Design Workflow with the Database Diary

In this blog, we take a look, not at a new command, but instead at a classic command…

• 2 min read
IC Packaging and SiP Design , documentation , IC Package , IC Packaging , packaging , Digital SiP design , IC Packaging and SiP , IC package design , APD , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , IC Package Physical layout and co-design

What's Good About Capture’s Update Cache? 16.6 Has a Few Enhancements!

The 16.6 OrCad Capture release now allows you to replace multiple cache parts in…

• 1 min read
PCB , capture , Cadence Design Systems , Allegro Design Entry , Allegro 16.6 , Design Entry CIS , cadence , OrCAD Capture , 16.6 , Capture CIS , Capture-CIS , SPB , OrCAD , PCB design , Design Entry , Grzenia , Allegro

Customer Support Recommended - Dimensioning in Allegro PCB Editor

Allegro PCB Editor offers drafting and dimensioning features that support electronic…

• 3 min read

What's Good About ADW’s Pull-Down Lists? 16.6 Has a Few New Enhancements!

The 16.6 Allegro Design Workbench (ADW) release now provides the ability to customize…

• 2 min read
Cadence Design Systems , Allegro 16.6 , cadence , DBeditor , 16.6 , property , Allegro Design Workbench , Library flow , selection filters , Library and design data management , SPB , design data management , Front-end PCB design , design , PCB design , Design Entry , Grzenia , Librarians , library , ADW , Allegro

What's Good About Allegro PCB Editor Shape Contraction and Expansion? Check Out 16

The 16.6 Allegro PCB Editor includes new enhancements to effectively manage shape…

• 3 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , PCB Editor , Layout , design , PCB design , Grzenia , physical layout design , Allegro PCB Editor , Allegro , etch shapes

Create Optimum Pin Assignments for FPGAs on PCBs - Part 2 of 2

In part 1 of this blog , I discussed a scenario that PCB designers working with FPGA…

• 5 min read
FPGA: ASIC Prototype , FPGA-PCB Co-Design , FPGA System Planner , FPGAs , FSP , pinswap , "PCB design" , OrCAD , PCB design , pin planning , pin swap , FPGA , Allegro , FPGA Pin Assignment , FPGA: PCB

How Do You Route Your Highly Constrained PCBs? (Part 1 of 2)

How routing is performed to meet the design intent of designers and engineers seems…

• 4 min read
interface aware design , DDR2 , Constraint-driven PCB Design flow , interconnects , Allegro 16.6 , Routing , route quality , 16.6 routing , interface definitions , interfaces , PCB Editor , PCB routing , Allegro router , "PCB design" , PCB design , Constraint Driven PCB routing , DDR3

Create Optimum Pin Assignments for FPGAs on PCBs - Part 1 of 2

In most FPGA-based boards, the PCB designer is on his own -- with little help from…

• 5 min read
FPGA: ASIC Prototype , FPGA-PCB Co-Design , FPGA System Planner , FPGAs , FSP , pinswap , "PCB design" , PCB design , pin planning , pin swap , FPGA , FPGA Pin Assignment , FPGA: PCB

What's Good About FSP’s Allegro PCB Editor Board Import? 16.6 Has It!

The Allegro FPGA System Planner (FSP) has the ability in the 16.6 release to import…

• 5 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , Taray , FPGAs , SPB , PCB Editor , Layout , design , FSP , "PCB design" , PCB design , Grzenia , Allegro PCB Editor , FPGA , Allegro , FPGA: PCB

Enhance Your Packaging Documentation Outputs with the New SKILL Spreadsheet API Tools…

Spreadsheets, we all use them, and many of us do so daily. They are an efficient…

• 3 min read
IC Packaging and SiP Design , SiP , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , IC Packaging and SiP , IC package design , APD , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , IC Package Physical layout and co-design , cavity

What's Good About Allegro PCB Enhanced Object Filtering? See for yourself in 16.6

The 16.6 Allegro PCB Editor release provides enhanced Object Filtering to control…

• 2 min read
PCB , PCB Layout and routing , Cadence Design Systems , diff pairs , constraint databases , Allegro GUI , Allegro 16.6 , cadence , DEHDL , electrical constraints , object visibility layers , 16.6 , property , diff pair , SPB , PCB Editor , Constraint Manager , Design Entry HDL , differential pair , Layout , Xnets , design , "PCB design" , PCB design , Design Entry , Constraints , Grzenia , Allegro PCB Editor , differential pairs , Differential Pair Support , ConceptHDL , PCB Capture , Allegro

What's Good About AMS Schematic Undo? It’s in the 16.6 Release!

Just a very brief post this week on a new AMS Simulator (PSpice) capability. The…

• less than a min read
capture , AMS , Allegro 16.6 , cadence , AMS simulator , OrCAD Capture , 16.6 , Capture CIS , PSPICE , OrCAD , AMS simulation , Grzenia

What's Good About RF PCB Libraries? 16.6 Has a Few New Enhancements!

There have been a few new library level enhancements made to 16.6 Allegro RF PCB…

• 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , RF PCB , cadence , Agilent , 16.6 , SPB , PCB Editor , Layout , design , PCB design , Grzenia , physical layout design , Allegro PCB Editor , Librarians , Agilent ADS , library

What's Good About PCB SI Channel Analysis? 16.6 Has Many New Enhancements!

There are several new enhancements associated with the 16.6 PCB SI Channel Analysis…

• 5 min read
PCB SI , SI , Cadence Design Systems , Allegro 16.6 , cadence , Signal Intregrity , SigXP UI , 16.6 , "PCB SI" , High Speed , SPB , signal integrity analysis , Signal Integrity , "channel analysis" , design , "PCB design" , Allegro PCB SI , Grzenia , SI analysis and modeling

What's Good About Allegro PCB Editor Parameterized Cornering? Check Out 16.6!

The Shape - Add Rectangle command has been enhanced in the 16.6 Allegro PCB Editor…

• 1 min read
polygon , PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , SPB , PCB Editor , setup , parameterized cornering , Layout , design , PCB design , Grzenia , Allegro PCB Editor , Allegro , etch shapes

What's Good About ADW’s Flow Manager? 16.6 Has Many New Enhancements!

The 16.6 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide…

• 2 min read
PCB , Allegro Design Entry , Allegro 16.6 , cadence , 16.6 , Directive Lockhing , Allegro Design Workbench , Library flow , color , Team design , Library and design data management , SPB , PCB Editor , Design Entry HDL , Layout , design , PCB design , Design Entry , Grzenia , ConceptHDL , library , Schematic , Allegro

Customer Support Recommended - Working with NetGroups in Allegro Design Entry CI…

Allegro Design Entry CIS provides a new feature called NetGroup, which offers an…

• 4 min read
PCB , Allegro 16.6 , Allegro Design Entry CIS , NetGroups , PCB design , vectors , buses , Schematic , hierarchical block , scalars , Allegro

Bending a Few IC Package Design Rules – With Confidence

Somewhere out there is an IC package designer who has been given design guidelines…

• 2 min read
PCB , IC Packaging and SiP Design , SiP , IC Packaging , Allegro Sigrity SI base , IC package design , APD , package design rules , physical layout design , XtractIM , PowerDC , PowerSI

What's Good About FSP’s Schematic Generation? 16.6 Has Many New Enhancements!

The 16.6 release of Allegro FPGA System Planner (FSP) has MANY new enhancements in…

• 4 min read
Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , FPGAs , Design Entry HDL , component browser , symbol , design , Grzenia , Librarians , library , Schematic , FPGA , FPGA: PCB

What's Good About Capture’s Find Command? 16.6 has a few new enhancements!

The 16.6 release of Alelgro Design Entry CIS (Capture) has added productivity enhancements…

• 1 min read
capture , Cadence Design Systems , Allegro 16.6 , Design Entry CIS , cadence , Find command , OrCAD Capture , 16.6 , Capture CIS , hierarchical schematics , SPB , Find result , design , OrCAD , Design Entry , Grzenia , PCB Capture , Schematic , Allegro

What's Good About DEHDL’s Hierarchical Split Symbols? The Secret's in the 16.6 Release

The complexity of the designs is constantly increasing and more and more logic is…

• 2 min read
PCB , split symbols , Allegro Design Entry , hierarchy , Allegro 16.6 , cadence , DEHDL , symbol editor , 16.6 , Library flow , hierarchical schematics , Library and design data management , Design Entry HDL , hierarchical split symbols , design , PCB design , Design Entry , Grzenia , Librarians , ConceptHDL , library , Schematic
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