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I read a recent article (June 11, 2009) in EDN magazine - "USB 3.0: A simple Idea Full of Challenges" by Ron Wilson.
In a nutshell, Ron says "Super-speed USB (Universal Serial Bus)
3.0 sounds like a great idea. Just start with widely used, fast, and
bulletproof USB 2.0 and graft in the PHY (physical-layer) interface
from another common and reliable standard, PCIe
(peripheral-component-interconnect express) Generation 2. Put two
differential pairs into the USB connector to carry the high-speed
serial signals from the Generation 2 PHY, and you have a rugged,
flexible, inexpensive interface that can operate at 5 Gbps over
consumer-priced cables and connectors with interfaces cheap enough to
drop into a flash drive."
"The idea promises to unleash new ways of using PCs with mobile devices
and with storage. With application-level throughput approaching 400
Mbytes/sec and the ability to simply plug anything from a flash drive
to 3m of USB cable into a host, usrs could link PCs and netbooks, quickly dump the contents of huge flash drives, or easily transfer HD (high-definition) video between devices. They could even create their own external storage networks (Figure 1). This promise of speed and flexibility, however, carries the seeds of a difficult challenge for chip, board, and system designers."Some of the challenges encountered are:
As for the timeframe to market "USB 3.0 will start out expensive, but, by 2011, it will probably be standard in netbook computers and handheld consumer products, such as cameras, media players, and flash drives.""One of the greatest differences between PCIe Gen 2 PHYs and USB 3.0 PHYs will be in the receiver-equalization circuit. Many designers expect the quality of this block to be a major differentiator in the market, for PHY-IP (intellectual-property), chips, and the systems that use them. The equalizer must be both powerful in its action and adaptive. Otherwise, a PHY would be unable to handle the range of channel conditions that USB can throw at it. As an adaptive equalizer, this circuit will require a training sequence to lock onto. Yet, the equalizer must be low in power and compact to meet the needs of consumer-product applications. Those challenges are formidable.""If a design team has really understood PCIe Gen 2, then they can adapt about 90% of their work to USB 3.0, says Scott Kim, manager of business development at Texas Instruments. Yes, the equalizer will need beefing up, but much of the circuitry will remain the same. For example, getting 5-Gbps performance from the PHY requires a careful trade-off between deep pipelining to meet throughput requirements and limited latency to meet bus timing."I'm curious about any experience you have with designing around the USB 3.0 protocol and what Cadence products/flows you're using to get past the design challenges.Jerry "GenPart" Grzenia
Thanks for the comments! Perhaps your design technique should become a USB 3.1 protocol - kidding, but not really. I wonder how difficult adjusting/tuning the implementation of the protocol is from a standards committee perspective? How can a designer propose improvements?
Should be great once the power and equalizer issues are resolved but I never did like the crude nature of the usb port. USB 3.0 should have an optical data link akin to the spdif ports on DVD players and perhaps only the power supplied via electrical contacts if there isn't a practical way of avoiding it. This should improve reliabilty and fault tolerance in addition to being more' 21st century'.