Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
In the SPB16.3 release, the SiP Layout Assembly Design Rules Checker (ADRC) User Interface has been integrated with the Constraint Manager will thereby become consistent with other design rule checks that use Constraint Manager technology. This also means that exporting the technology file from SiP Layout will save the Assembly Rule constraints to the Allegro technology file for reuse in other designs.
Assembly Design Rules
Checker. It is the feature described in this document.
Design Rule Check – A
requirement, be it physical, logical, electrical, etc. which the
final design must meet if it is to be properly manufactured into
a finished part.
constraint set (ACSet) is a named, reusable collection of
constraint values. There is no predefined default Assembly CSet.
The ADRC (Assembly Design Rule Checker) in SiP Layout is a batch process that is initiated after set-up via GUI and technology files. ADRC presents the user with a GUI consisting of one form. The user will select which rules should be checked. To set the constraints for each of the rules, a user should use the “Edit Constraints” button on the form to bring up Constraint Manager. On clicking the form’s “OK” button, the form is closed and the rules are run in a ‘batch’ mode, i.e. no further user interaction is required. Results of the rule checks are seen in both DRC markers placed in the design, and in an output report file as well as in Constraint Manager. Constraint manager could also be brought up using the regular toolbar and/or menu in SiP Layout.
Assembly Rule checks can be viewed as a batch DRC capability.While the interface itself can be edited in real time, once the rules are configured, it is a batch process to check the design and create any assembly DRC markers for the user.The performance of the actual checks will scale based on the size of the design, number, and complexity of rules being checked. Thus, a larger design will take longer to check, and it will take longer if you run more rules.The switch of constraints for ADRC over to using Constraint Manager and storing the constraints via standard Allegro technology should not cause a noticeable decrease in performance in SPB16.3 vs. SPB16.2.
The Standard Rules checker is intended for use as a batch command. Thus, the intent is for the user to set up and configure all the rules to be checked, and then spawn the batch process to perform all checks at once.
Assembly Constraint SetsThere are at least two scenarios where use of Assembly Constraint Sets are valuable:
Some users may want to support only two wire-to-wire spacing constraint values, one to use when the two wires belong to the same profile and the other when they belong to a different profile. Since the assembly rule check does not directly support this with different constraint values for the two cases, and easy way to do this is through use of a constraint set (cset), as follows:
Categories of different wire profiles sharing similar constraintsIf the design rules include one or more sets or categories of wire profiles that share similar constraint rules, you can create an Assembly Constraint Set for each category. The user can then put the constraint values for all of the relevant wire rules that a particular category of profiles would need to meet onto the specific category’s Assembly Cset in the Assembly Constraint Set Worksheets. Finally, go to the wire profile worksheets and for each wire profile that belongs to the category, set the Assembly Cset for that profile to the category’s corresponding cset.
Die ClassesBy default, the Die workseets will organize die constraints by listing all of the specific dies in the design. Constraint values can be applied to each die by referencing an existing Assembly Constraint Set (say a cset that you created called FLIP_CHIP, vs. one called WIREBOND) that contains the relevant constraint values. However, if there are many different csets in the technology, this can become a bit cumbersome, especially when the csets are brought in from a technology file. You can use die classes to provide an easier way to organize dies, and the organization can be saved to a tech file for easier reuse in other designs. For example, suppose you want to organize dies into two classes, one for wirebond dies and one for flip-chip dies. This can be done as follows:
Use Model Example for technology rules and constraintsIn order to set the constraints for the Assembly Rule checks:
For the Wire Rules, there are work pages: Wire Online Physical, Wire Online Spacing and Wire to Wire Online Spacing, Wire Physical and Wire Spacing. Choose the worksheet with the rule you would like to set constraint for. On the left, you can see all the available wire profile groups. Set the constraints for each of the Wire Profile Groups. If desired, use the Assembly Constraint Set Object to set constraints common to a few of the different wire profile groups. To use it, follow these steps:
5. When all the constraints for all the rules are configured, and if the constraints are applicable to the technology, save the technology file. From Constraint Manager, File->Export->Techfile
Menu and Command Line AccessThe Assembly Design Rules Checker can be accessed the same as in SPB16.2 via the “Manufacture” pull-down menu from the main tool bar (see figure below) or by command line. As in SPB16.2, if accessing by command line, use: assemrules standard.
In addition, new for SPB16.3 it can be accessed via “Setup” menu:
Graphical User InterfaceThe forms illustrated below show the fields of the user interface for this command.Figure A shows the form with no specific rule selected.Figure B shows an example of the form in use, where the picture and text have been changed to customize the form for the currently selected rule.
There is no mouse popup associated with the command, so this form is all that the user will see. The form and user interaction with the form, are the same in SPB16.3 as in SPB16.2, except where we note otherwise below. The individual fields are as follows:(Left side, top to bottom)
If you check the box beside a folder of rules, all rules in that folder would toggle to match the setting beside the folder. Thus, if you select and check the miscellaneous rules folder, all rules in this folder will become activated. Removing the checkbox from that field will, therefore, disable all the rules in the group. The same applies at the top level “All Rules” – checking this field will turn all rules in all folders on/off.(Right side, top to bottom)
(Buttons Along the bottom, left to right)
There are two groups of controls removed from the form since SPB16.2.:
Constraint Manager InterfaceIn constraint manager choose Assembly Rules domain. Select appropriate rules group and set / alter constraint for each of the rules in the group.In the Assembly Rules domain, Constraint Manager will have 4 objects: Assembly Constraint CSet, Wire , Die and Design.Wire rulesEach bond-wire object belongs to a wire profile group, and a single bond-wire cannot simultaneously be a member of more than one wire profile group. This will allow the user to set different constraint values for different wire profile groups for each rule. For each constraint there will also be a design level constraint that will be used for any wire profile that does not have a constraint value specific for that profile. We will not be supporting constraint overrides on specific bond-wires in SPB16.3 or connectivity objects such as nets of busesThere are 5 worksheets in the Wire Workbook : Wire Online Physical, Wire Online Spacing, Wire-to-Wire Online Spacing, Wire ADRC Physical and Wire Online Spacing.
For the Wire-to-Wire clearance rule, there will be a separate worksheet to set specific wire profile group to wire profile group spacing constraints. This allows specification of different spacing constraints between bond-wires belonging to any specific wire profile group and other bond-wires belonging to some other specific wire profile group.
All the die stack members: dies, interposers and spacers will be available to be added to user defined Die Classes. Similarly, to existing Net Classes in Constraint Manager, the user can create new Die Classes, giving them names. we will show the individual die stack objects (dies, interposers and spacers) as named objects (by reference designator) in the worksheet such that once a Die Class is created, the user can add die stack objects to the Die Class. The user interactions with the form and menus for creating and manipulating Die Classes will be the same as how Net Classes work today. We will not be supporting constraint overrides on specific die stack objects or connectivity objects such as nets and buses.
Design rulesFor all the rules that do not have any parameters dependencies, constraints should be entered at the design level.
Assembly Constraint SetAssembly constraint sets have been added for Wire and Die Rules. The user interaction to create and manipulate these constraint sets is the same as electrical constraint set in SPB16.2. Constraint sets are not available for design level constraints and layer based constraints in SPB16.3.
Technology FileThe constraints that drive the various rules supported by the ADRC tool are defined in a technology file. When writing the technology file, Constraint Manager writes all of the ADRC constraint IDs and constraint values into the technology file. In addition, the setting for which constraint ID rules should be run on the ADRC form will be stored in the technology file. This works exactly the same way as for existing electrical, spacing and physical constraint IDs.When loading a technology file, all ADRC constraints included in that file will update into Constraint Manager and the values seen in Constraint Manager’s worksheets will update. The next time the ADRC command is invoked, the form will now show the settings for which rules to run that were stored in the technology file.
Uprev and DownrevTo have designs in the SPB16.3 version and SPB16.2 compatible, an uprev from SPB16.2 to SPB16.3 is provided. The rules that were checked to be run will have the corresponding constraint ID in SPB16.3 enabled. All constraints from .ini file and .xml file would be read and moved to the appropriate constraint ID for SPB16.3 Constraint Manager.Uprev will also create new wire profile groups and constraint sets and map constraint sets to wire profiles in order to make wirebond constraints consistent with ADRC and the rest of the Allegro constraint system. In particular, if certain bond-wires do not match the wire diameter or material of their wirebond profile, uprev will create a new wire profile group for that and other matching bond-wires. In addition, if the XML file specifies constraints by non-profile properties such as wire diameter or material, uprev will create a wire constraint set to hold those constraints, and will apply that constraint set to all appropriately matching wire profiles that do not provide their own overriding constraint valuesDownrev would provide just limited capability. No .xml file will be written, but .ini file with design level constraints will be written.
Wirebond ConstraintsAll wirebond constraints, including online constraints have been added to constraint manager worksheets. The existing tab of the Analysis Modes form where online constraints are set in SPB16.2 were removed. All overlapping rules that are available in SPB16.2 in ADRC as well as online constraints are available as online rules only.
I look forward to your feedback!
Jerry "GenPart" Grzenia