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Fortunately, the folks working on TimingDesigner
and PCB SI
have been in close touch with each other and now provide a seamlessly integrated solution that allows straightforward timing closure on even the fastest
memory interfaces. When timing
violations are found, changes can be performed on the PCB design
re-analyzed without any translation making this two tool combination the
fastest path to timing closure.
Due to repeated requests for such a solution, a joint company (Cadence and EMA) webinar
will be broadcasted and recorded on June 9, 2010. Please
register at your earliest convenience
so that you will not miss the opportunity to watch and ask questions. Additional information and registration is
available from this link.
Let us hear your feedback on the webinar.
This is perfect for us! Maxwell86, does Timing Designer interface with the new Sigrity tools?
Hi Randy - the recorded webinar can be accessed at this address ... www.cadence.com/.../event.aspx
Hope to hear your feedback on the webinar.
When will it hit the archive, I missed it, heck.
Hi Waqar - We hope you will watch the webinar ... you will see the step by step procedure on how to use PCB SI and TimingDesigner to analyze and verify timing on DDR3 interfaces.
what is the porcedure