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This is second
in a series of blog posts about making your design cycles shorter and more predictable for
increasingly complex PCB designs. In my last post I talked about using
ECSets and Topology Apply capabilities for high-speed standards based
interfaces such as DDRx and PCI Express.
that theme, implementing high-speed signals can be a challenge as the delay
tolerances shrink and matching requirements increase.
example of differential pairs on advanced standards based interfaces (PCI
Express generation two and three). A few years ago, static phase tolerance from driver to
receiver was good enough. Now, with newer interfaces, differential pairs cannot
be out of phase over a certain length. A requirement like "differential pairs
can be out of phase by 20 mils for a running length of no more than 1/2” is
common in many designs. To manage such increasingly complex constraints, it is
important to arm yourself with a tool that provides “Dynamic Phase Control”
to implement fast, sensitive differential pairs.This Dynamic Phase control should be integrated with routing (interactive or automatic) of high speed differential pairs to accelerate correct-by-construction design completion.
Allegro PCB Design XL heads-up display for dynamic phase control accelerates creation of high-speed differential pairs
delay through a via is easy, but it should be integrated with the interactive
etch editing system to alert you immediately if Z-axis delay through the vias
is going to create a problem.
When it comes
to accounting for delays on matched signals inside the BGAs, Allegro PCB Design
XL suite allows users to manage it couple of ways. Users can import that delay
into Constraint Manger and then implement the PCBs. Another way is to annotate
such delays on the pins of BGAs when the BGA symbol is created and added to the
To learn more
about these capabilities, watch this archived webinar – Predictable,
Shorter Design Cycles for Dense, Complex PCBs.
Feel free to
comment on this or contact me directly via email – email@example.com