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Today at DesignCon, drop by the Cadence booth to see TeamAllegro demonstrate the new power delivery network (PDN) analysis technology for PCB design and analysis. This is important because higher speed technologies such as DDR3 require lower voltages. Lower voltages provide less margin for IR drop caused by power and ground planes that are carved up to meet design miniaturization requirements.
However, locating an IR drop problem is only half the battle. On a dense design, tradeoffs need to be performed to see how the IR drop problem can be resolved without impacting any design rules. The technology being demonstrated today will allow you to see how power and ground planes can be edited and re-analyzed without any translation. This provides a quick and efficient method to optimize planes and meet IR drop requirements with minimal PCB layers while meeting challenging PCB dimension specifications.Note this example of a PCB design where an IR drop problem has been caused by a combination of the etch shape on the plane and the perforation of the shape with vias from routing unrelated signals.
Once the problem is confirmed using the new Allegro PCB IR drop technology, the design can be edited and re-analyzed. Here we see with some minor edits, the IR drop in the area of concern is now within the required specifications.
Leave us your comments here to let us know what you thought
of the demo.