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Prior to the Allegro Package Designer (APD) 16.3 release, Design Rule Check (DRC) markers created by Assembly Rule Checks had to be external DRC markers since no constraint IDs were associated with the ADRC constraints. In the 16.3 release, Constraint IDs were created for each of the rules. It enabled us to make a change to DRC markers. For the 16.5 release, each Assembly DRC (ADRC) rule gets its own marker based on constraint ID.
APD’s ADRC DRC markers will look and behave similar to all DRCs. ADRC markers will differ for different rule checks (or groups of related rule checks), rather than all appearing the same as it was with using External DRC markers. ADRC DRCs will have their own worksheet in Constraint Manager instead of being combined with External DRC markers.
Differences between current (external) DRC behavior and constraint ID based behavior are as follows:
When object that has DRC Marker attached is moved
Marker stays at previous location (unattached )
will display the message that the disappeared marker doesn’t mean that there
is no error any longer, just that the ADRC rules have to be re-run.
have any effect on ADRC DRC markers
DRC will not affect ADRC DRC markers, similar to batch DRCs run by the rest
of the system
object that has DRC Marker attached is deleted
change in behavior
ADRC DRCs as any other in the system
change in behavior
Read on for more details ...
Show element difference
16.3: Constraint ID based in 16.5:
DRC marker difference
DRC marker 2 letter combinations Lower case letters for 2 letter combinations are used for the DRC bow-tie marker. Existing online wire rules already have 2 letter combinations and they are upper case letters. They are:
Wire Length ( minimum)
Wire Length ( maximum)
Wire Maximum Angle to Die Edge
Finger to Component Spacing
to Wire End Spacing
There are no changes to existing DRCs.
Rules in the group
2 letter combination
Wire Length over Parent Die
Wire Length over Lower Die
Wire Maximum Angle to Finger
Wire Substrate End Distance inside soldermask
Wire to Component Spacing
Die Pad Pitch
Die Pad To Lower Die Overhang
Die Pad to Upper Die Spacing
Die to Connected Finger Spacing
Die To Finger Spacing
Die to Package Edge Spacing
Die To Die Spacing, Connected Dies
Die To Die Spacing, Unconnected Dies
Wire to Die Pad Optical Short
Wire to Finger Optical Short
Wire To Wire Optical Short, Die to Die
Wire to Wire Optical Short, Die to Substrate
Center to Center Delta, Extends Based
Center To Center Delta, Pin Based
Stack to Die Stack Spacing
Die Flag to Die Flag Spacing
to Discrete Component Spacing
to Finger Spacing
to Package Edge Spacing
Solder Mask Coverage
Solder Mask Shape
Solder Mask Void
Mask To Die Edge Spacing
Mask to Package Edge Spacing
Mask To Solder Mask Spacing
Metal To Any Metal Spacing
to Package Edge Spacing
Component Pad to Finger Spacing
Component Pad to Package Edge
Metal to Exposed Metal Spacing
to Package Substrate Spacing
Extension from Finger
Package Substrate Edge Spacing
Angle Shape Boundary
Acute Angle Metal
Metal Minimum Angle
Minimum Angle to Pad
Minimum Angle to Shape
Minimum Angle to Trace
Shape Void Overlap
Please share your experience using this new capability.
Jerry "GenPart" Grzenia
APD is a design environment focused to a very "hot" topic today, the design and management of bare dies and electrical connections of them in the frame of advanced packages (SIP – System in Package, SOP - System on Package) and vertical stacked dice. A System-in-a-Package or System in Package, also known as a Chip Stack MCM, has a number of integrated circuits enclosed in a single package or module. The SIP performs all or most of the functions of an electronic system. System-On-Package (SOP) is the newemerging system technology that goes beyond System-On-Chip (SOC) and System-In-Package (SIP) and forms the basis of all emerging digital convergent electronic and bio-electronic systems.
The 16.5 APD addresses improvements of Assembly DRC (ADRC) rules, the new version increasing the capabilities to manage the errors and markers. For example, each Assembly DRC (ADRC) rule receives now its own marker based on a "constraint ID" in the Constraint Manager. In case of markers, the ADRC markers differ in 16.5 for different RC (rule checks) or groups of RCs. The ADRC markers have now a "personal" worksheet in the Constraint Manager, helping the designer to manage better the real cases and to understand easier the various problems which could appear in practice.
Furthermore, for electromagnetic investigation of dice and stacked-dice different methods could be used, as 2.5 D (3D layered) simulators based on Method of Moments or more general FEA simulators. The electromagnetic simulators offer today reliable results of SIP/SOP structures and help additionally the specialists using Cadence APD.
As a conclusion, APD 16.5 provides now a better interface with the designer in the field of ADRCs and management of errors and markers.