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All Allegro PCB Editor designers know about the uprev process to migrate PCB .brd files from prior SPB releases to a newer release. The Allegro Design Entry HDL (DEHDL) designers rarely need to uprev. With the 16.5 release, however, you will need to uprev designs.
The 16.5 release includes major architectural changes aimed at providing a Design Aware DEHDL with a dynamic connectivity model. In the new architecture, there is no need for design expansion and working at different modes. In order for any existing design to work in the 16.5 release, the design needs to be upreved. This uprev process will make the existing design compatible to work with the 16.5 release DEHDL software.
Read on for more details …
When you open any pre-16.5 release design in the 16.5 release, the tool auto-detects the need to uprev. The uprev utility is also available as a batch command and can be executed on the designs without opening the DEHDL schematic editor. You can also write some simple scripts and run the operation to uprev all the pre-16.5 designs. The process works like the Save Hierarchy operation. Each hierarchical block of the design is read and then upreved to the 16.5 release. The process is quite fast and the complete design hierarchy is updated to the 16.5 release.
Note: To open pre-16.5 release designs that have constraints on the schematic, you first need to synchronize the constraints. The designs will be upreved only after the constraints have been synchronized in the schematic using Tools> Constraints> Synchronize.
You can run the following command in batch mode to synchronize the constraints:concept2cm -proj <project.cpm > -export -forward -uprevThe uprev process does not modify any of the schematic sheets. However, you will notice that some changes have been made to the file structure. In the new architecture, Constraint Manager (CM) will be used for managing properties and constraints. All this information will now reside in a single database -- the CM database (*.dcf file). The CM database (*.dcf) file will now be stored in the sch_1 view only and therefore a "constraints" view is no longer required. Since the CM database (*.dcf) file will store the properties, there is no need for the viewprop.prp file in the sch_1 view and Occurrence Property (*.opf) file in the opf view. This leads to the elimination of two views – the constraints view and the opf view.
The requirement for generating and analyzing the Verilog netlist has also been removed from DEHDL. This has been made possible by the introduction of a new file which now stores the design connectivity. The design connectivity file is XML based file and will have the extension of 'xcon' (*.xcon). This file helps in loading the design with the complete design connectivity information very quickly and also enables incremental netlisting.
The table below summarizes the changes that occur to the schematic files:
The uprev process works similar to the File> Save Hierarchy process. The process visits each hierarchical block used in the design and uprevs them to the 16.5 release. The process is quite fast.
The following steps will guide you through the changes that occur when you uprev your design to the 16.5 release.1. Open an existing design in 16.5 release. The tool auto detects that the design is a pre-16.5 release design and prompts you to uprev the design with the following message dialog:
2. Click 'Yes' to start upreving the design. The process iterates over all the hierarchical blocks which have been used in the design and uprevs all the blocks to the 16.5 release.
Note: If there are errors during uprev, check the temp/csnetlister.mkr file for leads.
I look forward to your comments on DEHDL 16.5 upreving.
Jerry "GenPart" Grzenia
Thanks for your comments. There are enhancements that required the changes to the structure with the goal of minimal impact to what our customers need from the prior structure.
Let me know if there are specific issues you're encountering - I'll open a Case.
Why would you change anything (directory structure or files) until the user wants to change. Make temporary directories that are erased when exiting unless the user says "yes I want to update" Not a very smart programming move.
You can run Verilog, VHDL, PSpice, etc. simulations from the DEHDL schematic netlist. However, not from this native .xml file. Rather, a simulator specific netlist is generated depending on the desired simulator you're using.
Can this .xml based netlist be exported to virtuoso or can we ever run a simulation using this?
I would encourage you to please contact your local Cadence Customer Support region and work with a Customer Support AE on this issue. It appears to be specific to your design content and we'd need to review the design in more detail to determine the cause.
What if the person doesn't have the old release to synchronize the constraints before uprev? I have the problem that my 16.3 database was upreved and now all the constraints are attached to the nets and aren't visible in Constraint Manager. The constraints are being pushed to Allegro just fine, but Constraint Manager invoked from Allegro isn't showing the constraints either. I can see the constraints by looking at the properties of the nets.