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On day-two of the Cadence Signal and Power Integrity Three Day Event, it was standing room only as 100+ attendees listened in as Robert Hanson explained high speed interface design challenges associated with DDR3 and PCI Express 3.0. Robert took the mystery out of designing for timing compliance as well as how to meet bit error rate specifications on multi-gigabit interfaces.
Robert's material on multi-gigabit interfaces included a discussion on skin effect, dielectric loss and the need for pre-emphasis.
In addition, as multi-gigabit serial links are always implemented in differential pairs, Robert discussed some of the perils of poorly managed differential impedance.
Many of the attendees were able to stay for the afternoon workshops that
allowed hands-on experience with Cadence tools that analyze DDR3 and
PCI Express interconnect on PCBs.
This advanced Signal Integrity day gave attendees the unique opportunity
to learn the theory, get comfortable with the tools, and then take this
experience back to their workplace and apply immediately on designs in
process. Attendees that return for day-three will have the opportunity to learn about power delivery network (PDN) design and analysis and once again have an opportunity to get some hands-on experience with the Cadence tools that perform PDN anaylsis.
Let us hear about your experiences at day-two of the Cadence Signal and Power Integrity Three Day Event. A report on day one is located here.