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Components in a design communicate with each other based on some rules or protocols. These protocols contain a group of signals with some relationships defined between them -- for example byte lanes, clock and strobes. The Allegro Design Entry HDL 16.6 release enables the use of these protocols or signal grouping by introducing support for hierarchical interface definitions. These definitions can be entered in the design and can be saved on disk as a library for reuse purposes. This enables the system connectivity authoring at a higher level of abstraction, leading to acceleration in design intent authoring, and also communicates design intent at a higher level to the downstream processes. The grouping of signals can help in planning the PCB implementation by guiding placement and converting of the groups to bundles and help in routing of the board. It can also be used for IC-Package-Board co-design. Read on for more details …New objects have been introduced in the tools for supporting the design flow.Net Groups A Net Group is a collection of net objects which is hierarchical in nature. Different types of Net Objects, such as Nets, Buses, Differential Pairs, XNets, and Net Groups, can be added as members of a Net Group. However, any net object can be a member of one Net Group only. Similarly, a Net Group can be a member of only one Net Group.
Net Groups are created on the fly using the existing design signals. They provide a higher level of abstraction and replace User Defined Buses. Here’s an example of tapping from a Net Group:
Interfaces are library definition of Hierarchical Net Groups. They are defined using a special Interface Editor and can be stored on disk. They can be loaded from a formal definition on disk for instantiation in designs. The existing signals can then be mapped to the Interface instances using Auto Mapping or Manual Mapping.
Net Groups and instances of Interfaces can be used in the designs for faster design authoring.
The Old Model for representing an Interface: – Uses a Vector signal to model an Interface– Manually tap bits & enter signal name– Single Level of Grouping Only– Notes are used to map bits to signals– Common cause of connectivity errors
The New Model for representing an Interface– Leverage Hierarchical Net Group or Interface Object– No more manual mapping of signal to bit– Infinite hierarchical groups– Selection of members done using RMB menus
The new Design Entry HDL (DEHDL) Schematic Operations
– Creation of Hierarchical Net Groups • Schematic Selection • Editor Dialog box– Instantiation of Hierarchical Net Groups / Interfaces • Tapping out members for connectivity– Editing of membership of Hierarchical Net Groups– RMB menu provides access to all Net Group and Interface Members– Dynamic Net Group update by connecting named signal– Auto-naming using patterns– Navigation to instantiated objects– Synchronization & Cross-Probing with Constraint Manager ObjectsConstraints Manager Operations
– Creation of Hierarchical Net Groups– Editing of membership of non-schematic defined Hierarchical Net Groups– Constraining of Hierarchical Net Groups and Interfaces• Application of Constraints Set• Adding and overwrite of constraints
Interface-aware Placement and RoutingYou can display the shape of the auto-generated Interface and the Interface hierarchy can be traversed up / down:
You can do route feasibility analysis, and display the entire Interface at the RatBundle display. You can easily visualize scheduling issues. RatBundles can be edited (split, etc), but with limitations based on Interface hierarchy:
I look forward to your feedback!Jerry “GenPart” Grzenia