Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Feedback regulation loops are widely used by power electronic designers. It is one of the most important and sensitive parts of a power supply circuit. An incorrect feedback loop design may cause oscillations in the circuit, and also increase the output voltage droops. In order to achieve a stable and tight regulation in the output, it is important to have a correct feedback loop.
To test a feedback loop, generally engineers use trial and error methods with the hardware. This takes a lot of time and labor. Moreover, it is expensive because components and/or PCB boards can be damaged. AMS Simulator (also known as PSpice) can be used by designers to test their loop designs without using any physical hardware circuits, and in the process save a lot of time and cost that goes into fine-tuning the design.
You can get a copy of a sample regulation loop circuit created in PSpice along with the simulation results:
To download the Database (Created with Allegro Design Entry Capture) Click HereTo view the Datasheet Click Here
To demonstrate a regulation loop and compensator circuit, an example circuit is designed with the MAX8566 component and is available in the Cadence PSpice library.
There are two sections: Open loop design and closed loop design.
Open loop design
You can create an open loop design using the Cadence AMS Simulator (PSpice) tool. Using the component MAX8566 available in the Cadence PSpice library, and the datasheet for MAX8566, you can implement an open loop design as per the following figure:
In the open loop design there is no feedback. So the output will increase or decrease with the variation of input voltage. The output voltage is not controlled -- hence V(out) increases as the input voltage increases. The goal is to get a constant 1.9 Volts at the output with a variation of input from 2.3 Volts to 3.6 Volts.
The figure below shows the output voltage waveform when the input supply is at 2.3 Volts, and V(out) = 1.9 Volts
The figure below shows the output voltage waveform when the input supply is at 3.6 Volts, and V(out) = 2.94 Volts
So, the output voltage V(out) increases from 1.9V to 2.94V when the supply voltage increases from 2.3V to 3.6V.
Closed loop design
From the datasheet of MAX8566, Pin 2 is the error amplifier output and Pin 32 is the feedback input.Pin 25, REFIN, has the reference voltage, which is compared with feedback voltage (FB) to control the pulse width.
From the output filter the corner frequency of the circuit can be calculated as follows: fcorner=1/(2*Π*√L1*C1) Since C1 = 33μF, L1 = 200μH, fcorner ~= 2.0 KHz
The filter gives two poles at 2.0 KHz. These two poles produce a phase shift of 180° that makes the output oscillatory. Hence two zeros have to be introduced to cancel the complex poles at the corner frequency and another pole at the origin. This gives a single slope (-20dB/decade) crossing at the ‘0'dB axis, which makes the loop stable. The pole at origin also decides the bandwidth of the converter.
Following the above discussion compensator circuit should have Pole at ω = 0 Hz and Zero at ω = 2 KHz, 2 KHzConsidering all practical conditions, it is advised to choose the Zero location at 1/10th of the calculated value. For this design, Zeros can be considered at 200Hz. If the transfer function of the following circuit is derived, you can see that there are two zeros at fz1 and fz2 with one pole at fp where fz1 = 1/(2*Π*R37*C10)= 200Hz fz2 = 1/(2*Π*R32*C3)=200Hz fp = 0HzAfter doing all the above changes, the design is ready for closed loop simulation. If simulation is run, following results appear in the PSpice probe window.
The voltage at OUT is constant V(out) = 1.9 Volt.The user can vary the input supply from 2.3 Volt to 3.6 Volt. The output voltage will be constant at 1.9 Volt. There is no oscillation at output voltage and it is stable.Refer to the complete AppNote for a detailed procedure about each of the steps involved in the process.
Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).
do you have any in formation how to simulate organic thin film transistors
Thanks Frank for sharing the details from your website.
The example only seems to include simulations in the time domain but no simulations of the actual loop gain in the frequency domain. In other Cadence products, there are special analysis types for loop gain simulation: stb analysis in Spectre and pstb analysis in SpectreRF. My web page sites.google.com/.../loopgain presents some more information about loop gain simulation.