Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Beginning with the Allegro PCB Editor 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer types. Currently, a GCSF supports four types of layers: TOP, INTERNAL (internal signal), PLANE, and BOTTOM.
Importing a GCSF will not update the design’s cross-section, but will update the design’s constraint information (electrical, physical, and spacing) based upon the current import modes (overwrite, merge, and replace).When a GCSF is imported into a board, constraints from that techfile will be mapped as follows -1. TOP - TOP (topmost etch layer)2. INTERNAL - signal layers between TOP and BOTTOM3. PLANE - all plane layers4. BOTTOM - BOTTOM (bottommost etch layer)
Generating a GCSF
1. Open an existing board or create a new one and edit constraints.2. In Constraint Manager, use File > Export > (Technology file or Constraints file): 3. Select the “Generic” radio button in the “Export cross-section” section.The “Generic” radio button is enabled only if the “Physical & spacing constraints” box is checked.The “Configure” button is enabled only when the “Generic” radio button is selected.The “None” radio button is enabled only if “Physical & spacing constraints” box is not checked – otherwise cross-section data is necessary.4. Click the “Configure” button if you want to select the layers you would like to use as TOP, BOTTOM, INTERNAL, and PLANE (layer mapping): This step is optional. If generic cross-section is not configured, the default mapping will be used.User selections are remembered only for the current dialog form – when you invoke the export dialog again, the default mapping will be used.Default mapping: TOP: first etch layer
INTERNAL: first signal layer after TOP
PLANE: first plane layer
BOTTOM: last etch layerTo exclude a generic layer from the techfile, select <IGNORE>:In the situation shown in the screenshot above, the resulting generic techfile will have only three generic layers – TOP, PLANE, and BOTTOM.
Open Constraint Manager and select File > Import > (Technology file or Constraints file). Select the GCSF that you have exported from a different database and choose an Import Mode (overwrite, merge, or replace).If in the imported GCSF some of the generic layers are ignored, then layers matching the ignored layer will not be changed. This is what the report will look like: Note: When a GCSF is imported, the cross-section of the original board stays intact (i.e. the number of layers, their names, and characteristics remain as before importing; only the Csets are imported).The GCSF techfile units will behave the same way as any other techfile units. A suggested approach would be to have the same units used in both the original and the target board.I look forward to your feedback!Jerry “GenPart” Grzenia
Thanks for the comments Ulf! Almost all of the features I present in these Blogs are available from Cadence Online Support (http://support.cadence.com) in each product section's "What's New" area for a given release.
As in the past, a lot of the often very useful features of the Alegro suite are well kept secrets. I am amazed to learn that these features are rarely described in major release documentations but instead are "leaked" on user forums and using bulletins. But maybe it's just me that almost never visits the release events...