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The complexity of the designs is constantly increasing and more and more logic is being placed inside hierarchical blocks. This leads to an increase in the number of interfaces that are exposed by the hierarchical block. The increased number of interfaces means more pins are required on the block symbol. In many cases, the block symbols become so big (e.g. FPGAs, large pin count devices) that they cannot be placed on a standard page border. These large block symbols also become difficult to manage because of the many pins coming out of the same symbol. The 16.6 Allegro Design Entry HDL release provides a solution to better manage the hierarchical block symbols by splitting them into multiple split symbols. This has been an often requested enhancement! Instead of generating a big monolithic symbol, you have an option to split the ports of the hierarchical block over multiple symbols. This reduces the size of the block symbol. Also, the ports can be logically categorized and placed on different symbols to create symbols that can be placed across schematic sheets, especially near the circuitry to which they connect to. This makes placing the symbols much simpler and managing numerous pins easier.
This functionality is available in the 16.63 release.Read on for more details …
The Allegro Design Entry HDL (DEHDL) Component Browser now shows a hierarchical block’s split symbol viewing and instantiation:
Schematic operations include -
– The symbol version can be changed using the RMB Menu– Cut / Copy / Paste / Delete– Moving of split symbols across pages– Ascend / Descend Split Symbols – Highlight / Cross Probing There are several Hierarchy Viewer Operations:– Display a single entry for each block instance– Display a block identifier name (SPLIT_BLOCK_NAME)– Selection opened the first page of the block schematic instance– RMB Menus – All operations are the same – Select instance lists all split block instance symbols – Selecting an entry navigates to the selected block split symbol To generate a split symbol hierarchical block, you use Genview. There’s a new option to generate split symbols:
The distribution of pins across symbols can be done by using the Distribute Pins dialog or via Auto Distribution:
The Distribute Pins Dialog allows you to –
You also have the ability to use the command line genviewHDL command as well as importing via a text (.csv) file.I look forward to your feedback on experiencing this new capability!Jerry “GenPart” Grzenia
Hi Mike -
The example symbol above does show spaces or gaps between the pin stubs. GenView will not directly provide for gaps within the GUI/forms. You have two (2) options once the specific blocks are generated - you can either use the DEHDL Block > Move Pin command to move pins (if you're only moving a few pins), or preferably edit the symbol view and use the standard DEHDL commands (e.g. move, group) to move large groups of pins.
How do you insert spaces or gaps between ports with genview? Your example symbol shows them